GitHub - aryan-programmer/axi_gen_and_sum_primes_fpga: A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
.theia		.theia
array_accumulator		array_accumulator
array_axi_rw_vivado		array_axi_rw_vivado
array_writer		array_writer
debouncer		debouncer
decimal_digit_splitter		decimal_digit_splitter
edge_detector		edge_detector
four_digit_7_seg_driver		four_digit_7_seg_driver
led_slave_axi_to_wire		led_slave_axi_to_wire
led_switch_vivado		led_switch_vivado
seg_driver_clock_divider		seg_driver_clock_divider
switch_master_wire_to_axi		switch_master_wire_to_axi
wait_delay_timer		wait_delay_timer
.clang-format		.clang-format
.gitattributes		.gitattributes
.gitignore		.gitignore
.peers.ini		.peers.ini
.repo.yaml		.repo.yaml
array_axi_rw_design.pdf		array_axi_rw_design.pdf
common.hpp		common.hpp
simulation.hpp		simulation.hpp