Library for VLSI CAD Design Useful parsers and solvers' api are implemented.

Microshift Compression: An Efficient Image Compression Algorithm for Hardware

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

32-bit RISC-V microcontroller

Gatery, a library for circuit design.

This project was performed on the completion of our B. Tech 4th Semester Summer Training cum Academic Internship Programme on "RISC-V based 32-bit Digital Processor Design using SPICE" under E&ICT Academy IIT Guwahati and Assam Science & Technology University, Guwahati under TEQIP III in association with VLSI Expert

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

A simple tool to demonstrate the physical design steps of VLSI Design Flow.

Combinatorial and Decision Making Optimization (CDMO) project during the A.Y. 2021/2022.

Spiking Neural Network Accelerator

Domain Specific Hardware Accelerators - VLSI CAD Project

This repo contains golden vector and randomization testbenches for SRAM module.

FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)

This is a vlsi design of a hamming distance calculator circuit.

This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.