OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

my UVM training projects

Python implementation of the exact Riemann solver of Toro (1999).

Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI b…

Basics of UVM via an APB slave

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

NWPeval is a Python package designed to facilitate the evaluation and analysis of numerical weather prediction (NWP) models.

Verification, Validation, Uncertainty Quantification and Qualification Project

ATM-Utopia module and testbench.

An inference engine for Leon (https://github.com/epfl-lara/leon) that verifies resource bounds of functional Scala programs

This repo contains golden vector and randomization testbenches for SRAM module.

Example which helps understand modelling of a simple SV TB. For UVM implementation refer the repository "fifo_tb_uvm".

This repository hosts examples and documentation for System Verilog used for Testbench Development

This is Repo where the perfect functionality of the StackOverflow Implemented

JASP Verification Project

Lógica de Programación con KeY y Dafny

One App with the ability to register, search and remove the address records based on Latitude and Longitude! Involves the: 1. SQL Server and some methods to protect against SQL-injection, 2. Data security using salt hash, 3. two modes to operate such as Admin and user role, 4. Mailing and it’s 5. Multilingual using language resources.

Laravel Verification techniques Course on Udemy