SPM with DFT structure automatically injected by Fault
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Feb 14, 2021 - Verilog
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scan-chain
Here are 4 public repositories matching this topic...
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Dec 15, 2022 - Verilog
Post-manufacturing test analysis
compression decompression testing-tools fault-injection atpg bist jtag-boundary-scan mbist testability-analysis scan-chain fault-collapsing design-for-test
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Mar 27, 2024 - VHDL
VHDL circuit testing project featuring scan-based TRCUT architecture with testbenches, LFSR-based pseudorandom input generation, MISR-based signature analysis with fault injection (stuck-at and transient), and full IEEE 1149.1 (JTAG) implementation with TAP controller and boundary scan.
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Jul 10, 2025 - VHDL
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