Pinned

1. AUCOHL/Fault AUCOHL/Fault Public

   A complete open-source design-for-testing (DFT) Solution

   Swift 116 24

2. Fault-SPM Fault-SPM Public

   SPM with DFT structure automatically injected by Fault

   Verilog 5 1

3. Caravel-OpenFPGA-EF Caravel-OpenFPGA-EF Public

   Forked from efabless/caravel_mpw-one

   Verilog 8 1

4. HyBISCIS/MicroECT HyBISCIS/MicroECT Public

   Microscale 3-D Capacitence Tomography with a CMOS Sensor Array (BioCAS23)

   Python 2

5. efabless/caravel efabless/caravel Public

   Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

   Verilog 257 63

6. efabless/caravel_user_project efabless/caravel_user_project Public template

   https://caravel-user-project.readthedocs.io

   Verilog 170 322