WIP: Very much a RISC-V core, written in SystemVerilog
-
Updated
May 14, 2024 - SystemVerilog
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
WIP: Very much a RISC-V core, written in SystemVerilog
VSCode Devcontainer for WCH RISC-V microcontroller development
Nebula: a microarchitecture simulator built from loosely coupled microservices
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
The official repository for the gem5 computer-system architecture simulator.
RISC-V core virtual runtime written in C/C++ (Arduino platform) intended for ESP32-WROVER with PSRAM.
Lightweight justice for your single-board computer!
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
🚀 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
The main repository of CargOS
Functional verification project for the CORE-V family of RISC-V cores.
Speech-to-text, text-to-speech, and speaker recongition using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 servers, websocket server/client, C/C++, Python, Kotlin, C#, Go, NodeJS, Java, Swift
Open-source high-performance RISC-V processor