Open source ultrasound processing modules and building blocks
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Updated
May 8, 2024 - Jupyter Notebook
Open source ultrasound processing modules and building blocks
This project automates process of creating a PYNQ Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
Методические материалы по разработке процессора архитектуры RISC-V
DaCe - Data Centric Parallel Programming
FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket
🚀 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
HAL – The Hardware Analyzer
A truly open-source Camera serial interface with superb Signal Integrity. It's for Sony and affordable Series7 FPGA, eyeing Secure, HiRez video. All while improving openXC7, challenging its timing-savvy, and introducing lesser-known EU boards to open makers.
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
learn the combinational and sequential logic circuit.
Research and Materials on Hardware implementation of Transformer Model
RISC-V Linux SoC, marchID: 0x2b
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
HDL libraries and projects
The complete codebase for Frame
A set of Linux kernel drivers to support the LAWO Ravenna FPGA implementation, with Go bindings
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