This GitHub repository contains coursework projects related to computer systems design. It includes various assignments and projects that cover topics such as digital logic design, computer architecture, and hardware description languages. The projects are implemented using VHDL and may involve simulating and testing designs on FPGA boards or using VHDL simulators.
Welcome to the Computer Systems Design repository! This repository is dedicated to coursework materials and projects related to computer systems design. Here you will find resources and code examples covering various aspects of designing and implementing computer systems.
This section focuses on the fundamentals of digital logic design. It includes topics such as boolean algebra, logic gates, combinational and sequential circuits, and finite state machines.
The computer architecture section explores the organization and structure of computer systems. It covers topics such as processor design, memory hierarchy, instruction set architecture, and input/output systems.
In this section, you will find materials related to hardware description languages (HDLs). HDLs, such as VHDL and Verilog, are used to describe and model digital systems. This section provides examples and tutorials on using HDLs for system design.
The projects section contains hands-on projects that apply the concepts learned in the coursework. These projects may involve designing and implementing specific components of a computer system, such as a CPU, memory module, or an interface circuit.
Feel free to explore the resources and code examples in this repository. If you have any suggestions, feedback, or contributions, please feel free to contribute and help improve this repository. Happy learning and designing computer systems!