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130 Open 624 Closed
130 Open 624 Closed
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Issues list

cell-share Needs a Timing-Based Heuristic or Cost Model AMC Needed for Andrew's memory compiler C: calyx-opt Optimization or analysis pass
#2021 opened Apr 24, 2024 by andrewb1999
1
Separate Out FSM in IR when during TDCC and compile-static C: calyx-opt Optimization or analysis pass Status: Needs Triage Issue needs some thinking
#2020 opened Apr 24, 2024 by calebmkim
16
eDSL: reserved names, nonexistent ports C: calyx-py Items that have to do with the builder library Status: Available Can be worked upon
#2017 opened Apr 23, 2024 by anshumanmohan
2
Allowing invokes to pass in subtypes to ref cells C: Calyx Extension or change to the Calyx IL Status: Discussion needed Issues blocked on discussion
#2015 opened Apr 23, 2024 by nathanielnrn
1
[Profiling] Tracker Issue for Profiling first steps Type: Tracker Track various tasks
#2014 opened Apr 22, 2024 by ayakayorihiro
7 of 19 tasks
@ayakayorihiro
4
Do a Better Job At Removing Default Zero Assignments AMC Needed for Andrew's memory compiler
#2011 opened Apr 22, 2024 by andrewb1999
Queues: Rethinking our PIFO C: Queues One of the queue-style frontends Status: Available Can be worked upon
#1999 opened Apr 12, 2024 by anshumanmohan
@anshumanmohan
1
Eventually remove tests/xilinx/cocotb directory C: FPGA Changes for the FPGA backend Status: Blocked Issue is blocked
#1998 opened Apr 12, 2024 by nathanielnrn
Toplevel ref cells are not kept after compile_invoke pass C: Calyx Extension or change to the Calyx IL C: FPGA Changes for the FPGA backend
#1993 opened Apr 3, 2024 by nathanielnrn
Parse error for large constants
#1989 opened Mar 28, 2024 by Mark1626
2
Use External Libraries To Generate A Single Verilog File C: Verilog Status: In progress Issue is being worked on Type: Tracker Track various tasks
#1985 opened Mar 20, 2024 by jiahanxie353
Add CONTRIBUTING.md
#1981 opened Mar 20, 2024 by rachitnigam
1
New metadata format
#1979 opened Mar 20, 2024 by eliascxstro
1
2
Components that do a single read/write to a seq_mem generate circular combinational logic C: Calyx Extension or change to the Calyx IL Type: Bug Bug in the implementation
#1963 opened Mar 9, 2024 by nathanielnrn
2
Performance Dashboard Planning
#1960 opened Mar 6, 2024 by parthsarkar17
2
[fud2] Hypergraph C: fud2 experimental driver Status: Needs Triage Issue needs some thinking
#1958 opened Mar 5, 2024 by sampsyo
2
Toplevel ref cells interfere with static promotion C: Calyx Extension or change to the Calyx IL Type: Bug Bug in the implementation
#1956 opened Mar 4, 2024 by ayakayorihiro
4
seq-mem outputs xs when not explicitly assigning to write_en Type: Bug Bug in the implementation
#1955 opened Mar 4, 2024 by nathanielnrn
4
Calyx LSP Tracker / Wishlist C: calyx-lsp Language server issues Type: Tracker Track various tasks
#1951 opened Mar 1, 2024 by sgpthomas
3 tasks
Reorganize top-level folder
#1941 opened Feb 29, 2024 by rachitnigam
Make calyx-py AXI wrapper cocotb testbench accept yxi interfaces and dynamic input data C: FPGA Changes for the FPGA backend
#1938 opened Feb 28, 2024 by nathanielnrn
1
Change yxi backend to look for ref memories in addition to @external memories C: Calyx Extension or change to the Calyx IL C: FPGA Changes for the FPGA backend
#1932 opened Feb 24, 2024 by nathanielnrn
1
1
Calyx website revamp wishlist Type: Tracker Track various tasks
#1926 opened Feb 17, 2024 by rachitnigam
4 tasks
4
Report multiple errors C: Calyx Extension or change to the Calyx IL Status: Needs Triage Issue needs some thinking
#1924 opened Feb 16, 2024 by sgpthomas
5
Parameter-dependent attribute values C: Calyx Extension or change to the Calyx IL Status: Discussion needed Issues blocked on discussion
#1915 opened Feb 13, 2024 by rachitnigam
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