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Introduce verilog -> cocotb simulation fud2 path #1997

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Introduces a path accepting .v files, presumably axi-wrapped via a fud2 foo.futil --through axi-wrapped and outputting the final contents of AXI rams simulated via cocotb.

Invocation currently has to be manually specified due to the behavior of guess_state

An invocation looks like
fud2 <path to axi wrapped verilog> --from verilog-noverify --to cocotb-axi --set sim.data=<path to .data/json file>

This PR also introduces some cocotb python runners that largely looks like the xilinx cocotb harness. Those will hopefully be removed once we get the wrapper to properly interface with XRT.

@nathanielnrn nathanielnrn added the C: FPGA Changes for the FPGA backend label Apr 12, 2024
@nathanielnrn nathanielnrn added the C: fud2 experimental driver label Apr 12, 2024
@nathanielnrn nathanielnrn force-pushed the axi-fud2 branch 5 times, most recently from f0418a5 to 90fdfcf Compare April 22, 2024 20:29
Base automatically changed from axi-fud2 to main April 22, 2024 20:50
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Make calyx-py AXI wrapper cocotb testbench accept yxi interfaces and dynamic input data
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