eDSL: reserved names, nonexistent ports

[anshumanmohan]

Right now the eDSL lets you generate pretty free-wheeling Calyx, even if that Calyx is clearly wrong. I wonder how people feel about making the eDSL a little cleverer.

Below I refer to mwe.py; it generates mwe.yx.

Reserved Names

As we know, Calyx adds go and done ports to components so that they may be used as cells in multi-component designs. However, the eDSL happily lets you add ports with those very names.

calyx/calyx-py/test/mwe.py

Lines 4 to 7 in 148690e

	def insert_dummy_component(prog):
	comp = prog.component("dummy")
	comp.input("go", 1)
	comp.output("done", 1)

I don't know what Calyx would make of this; hopefully it would catch it and stop you from proceeding. However, I kinda think that the eDSL could just weed out some of this stuff if we teach it some rules.

Nonexistent Ports

The eDSL lets you assign to ports that don't exist.

calyx/calyx-py/test/mwe.py

Line 9 in 148690e

comp.this().flamingo = cb.HI

I regret to share that I don't actually have a port called flamingo on that component. Similarly, the eDSL lets you define a std_add called adder and then read/write to a port called adder.penguin. I think, when someone uses the {thing}.{port_name} notation to read from or write to a port, the eDSL could just check if thing actually has a port by that name. Another example of a thing that Calyx probably catches later on, but the eDSL is totally equipped to catch early on.

[rachitnigam]

Sounds like a good idea to me! Also, do you mind adding relevant labels to the issue ("calyx-py", "need triage / available")

[anshumanmohan]

Whoops mis-click...