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Verilog models (functional / timing) in Sky130 libs desired?

ubfx started Jan 9, 2024 in Development · Closed

3
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Support for VHDL

suppamax started Mar 9, 2022 in Development

21
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Equivalence check

suppamax started Mar 9, 2022 in Development

4
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Template Floorplan

AllenDBoston started Mar 21, 2022 in Development

1
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Using siliconcompiler with custom flow

gretzteam started Mar 8, 2022 in Development

3
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https://server.siliconcompiler.com/ doesn't resolve

stringinator started Dec 7, 2021 in Development

9