Equivalence check

[suppamax]

Hi,

does SiliconCompiler include an equivalence check RTL vs netlist and GDSII vs netlist?

[nmoroze]

Yep, to some extent!

We support LVS via Magic & Netgen for Skywater130. This can be activated by calling chip.set('flowarg', 'verify', 'true') before calling chip.load_target(...). test_gcd_skywater.py provides an example of how this works. Note that we are actively working on how the signoff aspect of the flow is being driven, however, so this interface will probably change over the next few days.

We also have support for doing RTL vs netlist LEC via Yosys, but it's in prototype stage. An example is here: https://github.com/siliconcompiler/siliconcompiler/blob/main/tests/tools/test_yosys.py.

[suppamax]

Thanks!

[jarvis-lorry]

Hi @nmoroze, I'm running the heartbeat example project with chip.set('flowarg', 'verify', 'true'). With the SiliconCompiler version 0.8.0, I no longer see the DRC or LVS files in the build directory. In previous SC versions, these were in the following two directories:
build/heartbeat/job0/drc/0/drc.log
build/heartbeat/job0/lvs/0/lvs.log

There's a drc report file in .../route... but it's an empty file.
build/heartbeat/job0/route/0/reports/heartbeat_drc.rpt

Here is my heartbeat.py:
import siliconcompiler # import python package

def main():
chip = siliconcompiler.Chip() # create chip object
chip.set('source', 'heartbeat.v') # define list of source files
chip.set('design', 'heartbeat') # set top module
chip.set('constraint', 'heartbeat.sdc') # set constraints file
chip.set('flowarg','verify','true')
chip.load_target('skywater130_demo') # load predefined target
chip.run() # run compilation
chip.summary() # print results summary
chip.show() # show layout file

if name == 'main':
main()

[nmoroze]

Hi,

In the current version of SC the signoff flow that runs DRC/LVS has been split off from the main ASIC compilation flow. For context, we are working towards supporting modular flows to give you the choice to run one or the other, or create a flow that combines both in one shot.

However, in the meantime you will have to run each one separately. There's some demo code for doing this here:
https://github.com/siliconcompiler/siliconcompiler/blob/main/examples/gcd/gcd_skywater.py.