XLS: Accelerated HW Synthesis
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Updated
May 9, 2024 - C++
XLS: Accelerated HW Synthesis
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Veryl: A Modern Hardware Description Language
SystemVerilog compiler and language services
A truly open-source Camera serial interface with superb Signal Integrity. It's for Sony and affordable Series7 FPGA, eyeing Secure, HiRez video. All while improving openXC7, challenging its timing-savvy, and introducing lesser-known EU boards to open makers.
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
Verilog code for fundamental combinational and sequential circuits
Verilator open-source SystemVerilog simulator and lint system
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