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288 Open 708 Closed
288 Open 708 Closed
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Issues list

Provide suggestName to Queue(and other Chisel Library Moduels)
#4055 opened May 5, 2024 by sequencer
1
provide an Chisel Native API for SystemVerilog bind
#4051 opened May 3, 2024 by sequencer
2
[Feature Request] expose outer class of ChiselEnum#Type
#4034 opened Apr 30, 2024 by Anillc
Connectable does not properly handle Views
#4024 opened Apr 23, 2024 by jackkoenig
Hard to obtain needed context to build IR for referencing results of FirrtlMemory
#4022 opened Apr 22, 2024 by SpriteOvO
2
Pass Chisel information to firtool to generate debug information for the Tywaves project
#4015 opened Apr 19, 2024 by rameloni
4 tasks
14
ProbeSpec and HarnessSpec tests fail
#4012 opened Apr 18, 2024 by rameloni
4
Printf to file
#3997 opened Apr 13, 2024 by sequencer
Bump Scalafmt
#3996 opened Apr 12, 2024 by sequencer
1
Chisel6.0 multiplication Width Lint Errors
#3994 opened Apr 12, 2024 by 2588469
1
Switch and only maintain mill build
#3991 opened Apr 11, 2024 by sequencer
1 of 11 tasks
Workspace path parsing fails on Windows
#3972 opened Apr 5, 2024 by zhc7
3
Add support for Scala 3
#3967 opened Apr 4, 2024 by Flowdalic
1
[Binder] Generate wrong IR in some cases of SInt
#3963 opened Apr 3, 2024 by SpriteOvO
1
@SpriteOvO
1
svsim: Verilator initial statements are not handled correctly
#3962 opened Apr 3, 2024 by ubfx
loadMemoryFromFile seems not work in chisel6.2.0
#3961 opened Apr 2, 2024 by yongruifang
3
Chisel Linker
#3959 opened Mar 31, 2024 by sequencer
@sequencer
[Feature Request/Proposal] Upstream Utils from rocket-chip into chisel where applicable.
#3954 opened Mar 27, 2024 by lordspacehog
1
[Feature Request] Raise an error if a property path is not hierarchically underneath the same owning module from Chisel bug
#3939 opened Mar 15, 2024 by SpriteOvO
5
<file>.v name appended to generated SV file when a blackbox is used
#3933 opened Mar 15, 2024 by wkkuna
2
node requested directionality on 'FlitTypes' must be hardware, not a bare Chisel type. Perhaps you forgot to wrap it in Wire(_) or IO(_)?
#3923 opened Mar 12, 2024 by TDppy
1
[Panama] Request to bind InstanceGraph API from CIRCT. Panama Related to Panama Binding Framework
#3767 opened Jan 25, 2024 by sequencer
@SpriteOvO
2
Memories are merge into single one after FIRRTL stage
#3739 opened Jan 14, 2024 by ardacekic
How to generate "only" verilog file when useing emitVerilog api
#3706 opened Dec 30, 2023 by Chiwawachiwawa
1
Request a DPI Intrinsic Module
#3678 opened Dec 6, 2023 by sequencer
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