Open Source Verilog Modules
-
Updated
Jan 25, 2023 - Verilog
Open Source Verilog Modules
This project is to design a processor and memory in the digital system design course at university.
Verilog design and testbench files for Flip Flop, Counters, RAM, FIFO, Shift Registers and other sequential logic circuits
Digital circuit description to perform multiplication with data_path and control_path using verilog
My ongoing practice verilog hdl codes.
A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
This project is done in Vivado in Verilog with hardware implementation and the project is optimized Schoolbook multiplier which is much faster than the traditional ones
Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator
simple system verilog example using an LFSR as the application
I am trying to develop my skills through daily practice and consistency.
<轻松成为设计高手: VerilogHDL 实用精解> EDA 先锋工作室, 王诚, 吴继华 2012.6
Traffic Light Controller using Verilog done in Vivado
my library of different digital hardware circuit designs and logic
This Repo consists codes for some the problem statements from the HDL BITS website and can help you in your journey to learn Verilog from the scratch
2-Term Karatsuba and 3-Term Karatsuba Algorithm on FPGAs in Vivado using Verilog with diffrent bits and with 3 diffrent method.
Add a description, image, and links to the verilog-code topic page so that developers can more easily learn about it.
To associate your repository with the verilog-code topic, visit your repo's landing page and select "manage topics."