Skip to content
View JAYRAM711's full-sized avatar
💯
DO SOMETHING GREAT
💯
DO SOMETHING GREAT
Block or Report

Block or report JAYRAM711

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned

  1. 100-DAYS-OF-RTL 100-DAYS-OF-RTL Public

    This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools

    Verilog 14 5

  2. FSM-MINI-PROJECTS FSM-MINI-PROJECTS Public

    This Repo contains Source Codes of FSM-BASED implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools

    Verilog 3

  3. FPGA-PROJECTS FPGA-PROJECTS Public

    This repository contains the files related to Implementations of various Digital circuits on the NEXYS A7 FPGA Board

    Tcl

  4. RISCV-MYTH-WORKSHOP/riscv-myth-workshop-sep23-JAYRAM711 RISCV-MYTH-WORKSHOP/riscv-myth-workshop-sep23-JAYRAM711 Public

    riscv-myth-workshop-sep23-JAYRAM711 created by GitHub Classroom

    TL-Verilog