All digital lowpas delta-sigma modulator (+digital up-converter) tune to fmax = 9 MHz
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Updated
Jan 15, 2018 - HTML
All digital lowpas delta-sigma modulator (+digital up-converter) tune to fmax = 9 MHz
Multi-level second-order (Silva Steensgaard Structure) delta-sigma modulator
Digilent Atlys Board Linux Flash Image
FPGA Tetris written in Verilog
Interfacing peripherals to FPGA
TOSLink fibre data capture for Pipistrello (Xilinx SPARTAN 6)
Verilog code that could run on Nexys3 (Spartan-6)
FPGA Messbauer hardware (generator, emulation of signal from gamma-source registered and amplified
This is the FPGA code for SSL bots , Robocup 2019
Paper soccer implementation by verilog on spartan6
This proyect is a game made with Verilog. Implementing a copy of the T-rex google game using an FPGA in a Spartan 6 with the use of VGA.
Creating a stack-attack like game for the Xilinx Spartan6 FPGA. A custom extension board was used for VGA control, created at BME. The program includes the VGA control hardware design, as well as software implementation in C. Use Xilinx ISE 14.7 and Xilinx SDK to compile.
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