RISC-V processor supporting Following Instruction sets R (Add,Mult,Sub) I (Immidiate value) S (Store)
the code is written in VERILOG Using XILINX ISE the code is for NEXYS 3 Spartan 6 FPGA Board the code have some errors i am working on it to make it work perfectly
The processor is created from the help of tutorials of RENZYM EDUCATION Computer Architecture Lectures by Yasir Javed This is my Digital Logic Design Semester Project Your support appreciated Thankyou