An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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Updated
May 16, 2024 - Scala
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Building one Solution for Threat management and detection for you network with Open source SOC solution.
Neural Turing Machine for a System on Chip verified with UVM/OSVVM/FV
Open source security data pipelines.
Code generation tool for control and status registers
Automate your SOC with SEKOIA.IO's Automation Library. Pull Requests are always welcome and highly appreciated!
This repository contain configurations files for Arcsight Flexconnector Regex file Type designed for Trend Micro InterScan Messaging Security Virtual Appliance (IMSVA)
Awesome list of keywords and artifacts for Threat Hunting sessions
Security lists for SOC detections
🚀 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
A textbook on system on chip design using Arm Cortex-A
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