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In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.
Implementing a subset of ARM instruction set architecture in a multicycle microarchitecture using Xilinx Vivado IDE. The computer architecture followed is Harvard (separate data and instruction memory).