This work is based on the following implementation from Benjamin Unger: 8-Bit Multicycle Processor Design and Implementation in Verilog.
I made my own SystemVerilog code based on the instruction set and diagrams exposed in the mentioned reference.
Instruction Opcode
- lw 0000
- sw 0001
- add 0100
- sub 0101
- j 1000
- jcz 1001
- jco 1010
- hlt 1011
The top module is CPUTopIO.sv. Check the constraint file to understand how are the leds, switches and displays wired to the CPU.
The demo program is called program.asm which is also compiled to binary in program.dat. This code will be automatically added to the RAM on synthesis, thanks to Vivado, so no need to manually feed the binary. Check the file Mem.sv and you will see the program is initialized in the initial block. Normally this block is considered only during simulation, but Vivado also allows to add data in some cases.
The cpu runs with a slow clock (1Hz) which allows to follow the fetch-decode-execute process with the eye. Anyways you can manually debug using the switch to enable/disable the clock at each step.