XLS: Accelerated HW Synthesis
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Updated
May 15, 2024 - C++
XLS: Accelerated HW Synthesis
DaCe - Data Centric Parallel Programming
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
FPGA Accelerator for CNN using Vivado HLS
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
Intermediate Language (IL) for Hardware Accelerator Generators
PandA-bambu public repository
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
Tutorials on HLS Design
CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
HeteroCL-MLIR dialect for accelerator design
A Vivado HLS Command Line Helper Tool
CHO is a benchmark suite for OpenCL FPGA Accelerators
A Compiler for the Popr Language
Polyphony is Python based High-Level Synthesis compiler.
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
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