high-level-synthesis
Here are 115 public repositories matching this topic...
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs
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Sep 13, 2022 - C++
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Oct 18, 2018 - C++
A MonteCarlo light propagation algorithm on a Xilinx FPGA using High Level Synthesis.
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Jun 6, 2017 - C
Convolutional Neural Networks for Verilog High-Level Synthesis
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Oct 19, 2018
Small designs made using Catapult-based HLS (C++ / SystemC)
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Feb 26, 2024
Laboratory exercises on cards with ARM, FPGA and sensors
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Mar 23, 2021 - C
Algorithmic Design of Digital Systems - Autumn Semester 2023 - Indian Institute of Technology Bombay
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Dec 3, 2023 - Makefile
Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis
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Apr 11, 2024
Kiwi was developed at the University of Cambridge Computer Laboratory and Microsoft Research Limited, headed by **David Greaves (UoCCL)** and **Satnam Singh (MRL)**
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Sep 5, 2022 - Verilog
Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)
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Feb 17, 2024 - C++
Transpiles a subset of Python functions into synthesizable SystemVerilog.
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Mar 8, 2024 - Python
Repository of DB4HLS. A database of design space exploration in high-level synthesis.
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Jan 5, 2021 - Python
Master thesis project - Comparing a FM Radio implementation in VHDL versus high-level synthesis (HLS).
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Sep 30, 2021 - VHDL
[FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
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Feb 14, 2023
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Apr 11, 2019 - C
C++ code generation tools for real-time CPU or FPGA simulation solvers of electrical and power electronic systems. To cite this software publication: https://www.sciencedirect.com/science/article/pii/S2352711021000054
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Oct 13, 2020 - C++
high abstraction synthesis
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Apr 8, 2024 - Python
Design of High-Level Synthesis of Xilinx FFT IP core via FFT library
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Jul 17, 2023 - Tcl
Personal blog on GitHub
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Jul 25, 2017 - HTML
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