A textbook on system on chip design using Arm Cortex-A
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Updated
May 14, 2024
A textbook on system on chip design using Arm Cortex-A
RISCV CPU implementation in SystemVerilog
The Task Parallel System Composer (TaPaSCo)
RISC-V is an open-source instruction set architecture (ISA), enabling the implementation of central processing units (CPUs) or system-on-a-chip (SoC) designs without licensing fees. This makes it highly favored among FPGA enthusiasts for softcore processor implementations.
Tutorial and base project: TEE on AMD Zynq UltraScale+ using Arm TrustZone
A SoC implementation of a PDP-8/I for the PiDP-8/I console
Trabalho final de conclusão de curso em Ciência da Computação.
Up-to-date [SIGCOMM 2023] Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference
Intel Quartus Prime Synthesis Engine for Docker
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.
Public Domain Computer on FPGA
An implementation of the RISC stack ISA spec from ISA-docs
SoC and Embedded Linux
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