Gain an understanding of the fundamental topics and concepts of computer architecture including the application of these with modern Arm processors

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

A textbook on understanding system on chip design

VHDL , ModelSIM, Quartus, FPGA, Image Processing

The Sherwood Architecture is a custom 64-Bit RISC based CPU architecture.

Μια ενδεικτική υλοποίηση RISC-V επεξεργαστή και ενός υποστηρικτικού Assembler - Διπλωματική εργασία στο Τμήμα Μηχανικών Η/Υ και Πληροφορικής, Πανεπιστήμιο Πατρών / An Indicative RISC-V CPU Implementation and an Accompanying Assembler - Master's Diploma Thesis at the Computer Engineering and Informatics Department (CEID), University of Patras

the Stupidest CPU Arch Possible

[2009 – 2012] MDSP: functional simulation of a Multimedia Digital Signal Processor

Code snippets for the CpuFun blog

General purpose processor with a RISC architecture and a five stage pipeline, implemented on a Cyclone IV FPGA using a development board

[Computer Engineering] Programmable 8-bit computer based on von Neumann architecture, designed and implemented from scratch in Logisim.

Tomasulo algorithm visualizer

RISC-V CPU arhitecture

The virtual CPU (and emulator) built for hobbyists

První projekt (CPU s brainfuck-like ISA) z předmětu Návrh počítačových systémů (INP), třetí semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023

My semester-long project for CS261 - Computer Systems at James Madison University where I constructed a cpu simulator using a smaller version of x86 called y86.

Basic VHDL projects gradually creating a pipelined CPU running Charis4 instruction set.

A 16 bit SAP-1 CPU that I designed in grade 10 designed in logisim

a smiple 8bit cpu implemented in verilog and tested on FPGA for understanding how CPU works