RISC_V

RISC V procesor arhitecture made in Vivado, capable of arithmetic operations using a pipeline.

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
.gitattributes		.gitattributes
ALU.v		ALU.v
ALUcontrol.v		ALUcontrol.v
EX.v		EX.v
EX_MEM_reg.v		EX_MEM_reg.v
ID.v		ID.v
ID_EX_reg.v		ID_EX_reg.v
IF.v		IF.v
MEM_WB_reg.v		MEM_WB_reg.v
PC.v		PC.v
README.md		README.md
adder.v		adder.v
control_path.v		control_path.v
data_memory.v		data_memory.v
forwarding.v		forwarding.v
hazard_detection.v		hazard_detection.v
if_id_pipe.v		if_id_pipe.v
imm_gen.v		imm_gen.v
instruction_memory.v		instruction_memory.v
mux2_1.v		mux2_1.v
mux_4_1.v		mux_4_1.v
registers.v		registers.v
risc_v.v		risc_v.v

SexySparrow/RISC_V