The repository hosts an ongoing project dedicated to the development of an implementation for the Advanced Encryption Standard (AES) 128-bit block cipher in UART communication. Please be advised that this project is currently in progress and subject to updates.

The Bosch BMP280 temperature and pressure sensor is connected to an STM32 microcontroller using low-level register-based programming via two distinct protocols: I2C and SPI. The sensor's data is then showcased on a 16x2 LCD display, which is also linked to the STM32 microcontroller.

PROFINET device stack for embedded devices

Not only IP Chat

Portable reference implementation of the Cyphal protocol stack in C++ for embedded systems and Linux.

Open-source and real-time orchestrator for cyber-physical-systems, to easily design, test and deploy embedded applications and digital twins.

Python implementation of the Cyphal protocol stack.

Library for ESP8266 is a simplified and user-friendly version of the "espnow.h" library.

Formal specification and generation of verifiable binary parsers, message generators and protocol state machines

A compact implementation of the Cyphal/CAN protocol in C for high-integrity real-time embedded systems

A Light of Things (LoT) Transmitter-Reciever System implemented using STM32f0Discovery boards.

Implementation of the performance evaluation of "On the Impact of Control Signaling in RIS-Empowered Wireless Communications"

An UART Receiver that runs with a clock frequency of 125 MHz. The possible baudrates are 9600 bits per second and 115200 bits per second. It supports the parity bit. The received bytes are stored in a FIFO buffer with variable size.

A simple, fast approach to implement your communication protocol.

Chat using „enhanced“ end-to-end-enryption and modulation of audio signal in isolated device, ensuring privacy, anonymity and cybersecurity.

3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.

FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.

CommsDSL schema-based definition of UBLOX protocol

CommsDSL schema-based definition of MQTT v5 protocol

CommsDSL schema-based definition of MQTT-SN protocol