Skip to content
#

arty-s7

Here are 8 public repositories matching this topic...

Language: All
Filter by language

FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.

  • Updated Apr 13, 2024
  • VHDL

Improve this page

Add a description, image, and links to the arty-s7 topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the arty-s7 topic, visit your repo's landing page and select "manage topics."

Learn more