Burp Plugin to decrypt AES encrypted traffic on the fly

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

Two scripts in Python to encrypt/decrypt using the 128 bits AES algorithm, ECB mode with hex "00" as padding for each character. For the encryption, an ascii plaintext file is taken as the input, then an encrypted hex file is outputted. For the decryption, a ciphertext hex file is taken as the input, then a decrypted ascii file is outputted.

The Most Pythonic M3U8 Playlist Parser and Downloader Allowed by Law. Automatic AES Decryption. All HLS Tags Are Supported. All SCTE-35 Tags are Supported.

Flask website for implementation of paper on text-based steganography i.e. hiding a secret message in a cover message and sending it over social media which in turn can be revealed.

Configurable AES-GCM IP (128, 192, 256 bits)

GPP CPassword Decryption Tools

A Lightweight Single Header file C++ AES Library that also supports AES Hardware Acceleration Technology

Reads the power meter (every 10 sec.) de-crypt and publish to the MQTT server

Golang programs for AES-CTR mode encryption with 2 different hashing algorithm and Padding Oracle attack on AES-CTR mode.

GoLang Crypto operations - AES, HMAC, Checksum and RSA Encrypt Decrypt

Ace Pradator is a Drive Encrypter which Encrypits on basis of AES Algorithm And thus it Protect The Data From Reading

Lightweight AES for C++11 | ECB | CBC | CTR | OFB | CFB | CFB8 | CFB1

AES Encryption and Decryption implementation for CT303 - Basis of Information Integrity and Security - Academy of Cryptography Techniques

Implementing AES and TDES with CryptoPP Library

Simple AES Cipher made in python for educational purposes.

Android AES-ECB/CBC, reference implementation by me in Java for PGSS.

Accelerate AES by opencl

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog

implementing a protected communication platform between 2 FPGA's. Data is entered through a keyboard-FPGA interface then the data is encrypted using AES encryption and sent to the second FPGA where the decryption occurs if the decryption key is given and the data is displayed using an FPGA-LCD interface using VHDL scripts