bluespec
Here are 34 public repositories matching this topic...
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
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Sep 15, 2023 - Bluespec
P4-14/16 Bluespec Compiler
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Dec 26, 2017 - Bluespec
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
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Feb 29, 2024 - Coq
Altera JTAG UART wrapper for Bluespec
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Mar 27, 2014 - C
Translates Bluespec SystemVerilog to Kami for use with the coq proof assistant.
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Oct 13, 2021 - Python
Bluespec SystemVerilog implementation of the Keccak primitive (SHA-3)
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Dec 27, 2015 - Bluespec
Domain Specific Hardware Accelerators - VLSI CAD Project
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Jan 11, 2021 - Bluespec
Forth CPU J1 in Bluespec SystemVerilog (BSV)
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Apr 30, 2023 - Verilog
Altera JTAG Source/Probe wrapper for Bluespec
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Apr 9, 2014 - Tcl
BlueSpec Verilog Syntax Highlighting for Notepad++
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Nov 29, 2018
Low-cost modular acquisition and stimulation system for neuroscience
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May 7, 2015 - Bluespec
Bluespec System Verilog syntax highlighting for Notepad++
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Jun 27, 2023
Hardware implementation of Lightweight Cryptography candidates in Bluespec SystemVerilog.
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Jun 29, 2023 - C
RISC-V cores based on Bluespec's Piccolo and Flute
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Jul 3, 2020 - Python
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