Skip to content
View GnosGnas's full-sized avatar
😴
😴
  • IIT Madras
  • Chennai
Block or Report

Block or report GnosGnas

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories

  1. Hardware-Modeling-using-Verilog Hardware-Modeling-using-Verilog Public

    Solutions to programming assignments of NPTEL course - Hardware Modeling using Verilog

    Verilog 3

  2. Side-Channel-Analysis Side-Channel-Analysis Public

    Repository for various experiments done during Aug'21 to Mar'21 related to Side-channel-analysis of Shakti's AES accelerators

    Verilog 3 3

  3. AES-accelerator-with-PICOrv32 AES-accelerator-with-PICOrv32 Public

    EE2003-Final Project: Hardware Accelerator for AES

    Verilog 3

  4. Shakti-Projects Shakti-Projects Public

    Projects done under SHAKTI, India's first indigenously developed and manufactured microprocessor

    Bluespec 2

  5. EE2003-Computer-Organisation EE2003-Computer-Organisation Public

    Solutions to assignments of ee2003

    Verilog 2

  6. Verilog-Projects Verilog-Projects Public

    C 1