Pull requests: SpinalHDL/SpinalHDL
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Constraint writer for Xilinx Vivado (reopened: CDC rework)
#1369
opened Mar 20, 2024 by
KireinaHoro
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Ability to remap address for BusSlaveFactory
#1354
opened Mar 13, 2024 by
KireinaHoro
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Draft
2 tasks
jtagvpi: Don't use blocking IO, to avoid blocking the simulation
#1350
opened Mar 12, 2024 by
rpls
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2 tasks
SpinalFormalConfig: Set _hasAsync accodring to clock config; set includeFormal as default in SpinalFormalConfig
#1320
opened Feb 20, 2024 by
janschiefer
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1 task done
Verilog generated when using synchronous resets is not understood by SymbiYosys - remove "assert() else begin end"-block generation for now
#1315
opened Feb 19, 2024 by
janschiefer
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[feature] FuseSocGeneratorBuilder provide a easy way to use fusesoc
#1232
opened Nov 2, 2023 by
chenbo-again
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feat: add loadHex function for SparseMemory
#1015
opened Jan 12, 2023 by
hanm2019
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1 of 2 tasks
Add ethernet udp tx/rx module
feature ✨
Feature idea with clear API defined
wontfix
The issue would not be fixed
#1010
opened Jan 10, 2023 by
jjyy-Huang
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1 of 7 tasks
feature: add new optional reset signal to StreamWidthAdapter and StreamFragmentWidthAdapter
#1008
opened Jan 8, 2023 by
jonnykl
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2 tasks
Memory: multiple ports with writeFirst should be permited.
#678
opened Apr 6, 2022 by
nbstrike
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[RFC] Add support for multiple CS pin for SDRAM controller
#577
opened Jan 10, 2022 by
t123yh
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