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99 Open 560 Closed
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Issues list

Linux: Spaces in path break formal verification
#1408 opened May 6, 2024 by TheImunityGamer
1
Seed does not work at parallel test of spinal sim
#1406 opened May 6, 2024 by developfpga
1
Can't infer width of Payload
#1404 opened Apr 29, 2024 by NikLeberg
2
Support for memories with read latency higher than 1
#1392 opened Apr 22, 2024 by fayalalebrun
18
Slower on the intranet network
#1391 opened Apr 21, 2024 by balanx
9
Are there some bugs in clockDomain.waitSampling() API?
#1382 opened Apr 7, 2024 by yuqi-ali
10
Blackboxing RAM with one read and one readWrite port
#1372 opened Mar 21, 2024 by KireinaHoro
2
JTAG VPI Simulation gets blocked by IO
#1349 opened Mar 12, 2024 by rpls
1
2
assignDontCare on Bundle element inside Union does not work
#1337 opened Mar 4, 2024 by KireinaHoro
14
SpinalSim: onSamplings can't work properly with clock from a blackbox
#1334 opened Mar 3, 2024 by zyn810039594
8
Plugin deadlock in circular dependency on Handle
#1331 opened Feb 28, 2024 by KireinaHoro
5
Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys
#1314 opened Feb 19, 2024 by janschiefer
10
WishboneSlaveFactory - doWrite is never called in pipelined mode
#1310 opened Feb 13, 2024 by janschiefer
1
3
StreamFragmentWidthAdapter.make missing earlylast argument
#1303 opened Feb 6, 2024 by louiecaulfield
2
question about mem initialization
#1302 opened Feb 6, 2024 by damaoew
11
ClockDomain for input/output ports?
#1299 opened Jan 30, 2024 by KireinaHoro
10
Is there any way to add delay at assignment?
#1296 opened Jan 29, 2024 by developfpga
5
Axi4Stream user signal width should not be multiplied by data width
#1294 opened Jan 23, 2024 by KireinaHoro
1
Warn / prohibit using SlowArea clock wire
#1287 opened Jan 18, 2024 by louiecaulfield
4
Playing around spinal in scala console fails
#1284 opened Jan 17, 2024 by soartang
6
Reg(False) / Reg(True) are valid statements
#1280 opened Jan 12, 2024 by dnltz
3
Fix nameless enum in VHDL
#1267 opened Dec 29, 2023 by Dolu1990
Explain the lib：Apb3SpiXdrMasterCtrl.scala and SpiXdrMasterCtrl.scala
#1263 opened Dec 18, 2023 by Amegodvivado
1
Documentation / example usage for Axi4ReadOnlyMasterAgent and Axi4WriteOnlyMasterAgent
#1261 opened Dec 14, 2023 by KireinaHoro
5
Arbitrary data bundle type for Axi4Stream
#1254 opened Dec 6, 2023 by KireinaHoro
12
ProTip! What’s not been updated in a month: updated:<2024-04-08.