Upload TARGET_CY8CPROTO-063-BLE 2.0.0.17932

COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

@@ -4,11 +4,13 @@
 * Description:
 * Wrapper function to initialize all generated code.
 * This file was automatically generated and should not be modified.
-* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.6.0.4266
+* Tools Package 2.2.0.2801
+* latest-v2.X 2.0.0.6211
+* personalities 3.0.0.0
+* udd 3.0.0.562
 *
 ********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
+* Copyright 2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

@@ -4,11 +4,13 @@
 * Description:
 * Simple wrapper header containing all generated files.
 * This file was automatically generated and should not be modified.
-* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.6.0.4266
+* Tools Package 2.2.0.2801
+* latest-v2.X 2.0.0.6211
+* personalities 3.0.0.0
+* udd 3.0.0.562
 *
 ********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
+* Copyright 2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

@@ -4,11 +4,13 @@
 * Description:
 * Sentinel file for determining if generated source is up to date.
 * This file was automatically generated and should not be modified.
-* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.6.0.4266
+* Tools Package 2.2.0.2801
+* latest-v2.X 2.0.0.6211
+* personalities 3.0.0.0
+* udd 3.0.0.562
 *
 ********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
+* Copyright 2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

@@ -5,11 +5,13 @@
 * Contains warnings and errors that occurred while generating code for the
 * design.
 * This file was automatically generated and should not be modified.
-* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.6.0.4266
+* Tools Package 2.2.0.2801
+* latest-v2.X 2.0.0.6211
+* personalities 3.0.0.0
+* udd 3.0.0.562
 *
 ********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
+* Copyright 2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

@@ -4,11 +4,13 @@
 * Description:
 * Peripheral Hardware Block configuration
 * This file was automatically generated and should not be modified.
-* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.6.0.4266
+* Tools Package 2.2.0.2801
+* latest-v2.X 2.0.0.6211
+* personalities 3.0.0.0
+* udd 3.0.0.562
 *
 ********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
+* Copyright 2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -27,7 +29,7 @@
 #include "cycfg_peripherals.h"
 
 #if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_BLE_obj =
+	const cyhal_resource_inst_t CYBSP_BLE_obj = 
 	{
 		.type = CYHAL_RSC_BLESS,
 		.block_num = 0U,

COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

@@ -4,11 +4,13 @@
 * Description:
 * Peripheral Hardware Block configuration
 * This file was automatically generated and should not be modified.
-* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.6.0.4266
+* Tools Package 2.2.0.2801
+* latest-v2.X 2.0.0.6211
+* personalities 3.0.0.0
+* udd 3.0.0.562
 *
 ********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
+* Copyright 2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

@@ -4,11 +4,13 @@
 * Description:
 * Pin configuration
 * This file was automatically generated and should not be modified.
-* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.6.0.4266
+* Tools Package 2.2.0.2801
+* latest-v2.X 2.0.0.6211
+* personalities 3.0.0.0
+* udd 3.0.0.562
 *
 ********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
+* Copyright 2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -26,7 +28,7 @@
 
 #include "cycfg_pins.h"
 
-const cy_stc_gpio_pin_config_t WCO_IN_config =
+const cy_stc_gpio_pin_config_t WCO_IN_config = 
 {
 	.outVal = 1,
 	.driveMode = CY_GPIO_DM_ANALOG,
@@ -43,14 +45,14 @@ const cy_stc_gpio_pin_config_t WCO_IN_config =
 	.vohSel = 0UL,
 };
 #if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t WCO_IN_obj =
+	const cyhal_resource_inst_t WCO_IN_obj = 
 	{
 		.type = CYHAL_RSC_GPIO,
 		.block_num = WCO_IN_PORT_NUM,
 		.channel_num = WCO_IN_PIN,
 	};
 #endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t WCO_OUT_config =
+const cy_stc_gpio_pin_config_t WCO_OUT_config = 
 {
 	.outVal = 1,
 	.driveMode = CY_GPIO_DM_ANALOG,
@@ -67,14 +69,14 @@ const cy_stc_gpio_pin_config_t WCO_OUT_config =
 	.vohSel = 0UL,
 };
 #if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t WCO_OUT_obj =
+	const cyhal_resource_inst_t WCO_OUT_obj = 
 	{
 		.type = CYHAL_RSC_GPIO,
 		.block_num = WCO_OUT_PORT_NUM,
 		.channel_num = WCO_OUT_PIN,
 	};
 #endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t SWDIO_config =
+const cy_stc_gpio_pin_config_t SWDIO_config = 
 {
 	.outVal = 1,
 	.driveMode = CY_GPIO_DM_PULLUP,
@@ -91,14 +93,14 @@ const cy_stc_gpio_pin_config_t SWDIO_config =
 	.vohSel = 0UL,
 };
 #if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t SWDIO_obj =
+	const cyhal_resource_inst_t SWDIO_obj = 
 	{
 		.type = CYHAL_RSC_GPIO,
 		.block_num = SWDIO_PORT_NUM,
 		.channel_num = SWDIO_PIN,
 	};
 #endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t SWCLK_config =
+const cy_stc_gpio_pin_config_t SWCLK_config = 
 {
 	.outVal = 1,
 	.driveMode = CY_GPIO_DM_PULLDOWN,
@@ -115,7 +117,7 @@ const cy_stc_gpio_pin_config_t SWCLK_config =
 	.vohSel = 0UL,
 };
 #if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t SWCLK_obj =
+	const cyhal_resource_inst_t SWCLK_obj = 
 	{
 		.type = CYHAL_RSC_GPIO,
 		.block_num = SWCLK_PORT_NUM,

COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h

@@ -4,11 +4,13 @@
 * Description:
 * Pin configuration
 * This file was automatically generated and should not be modified.
-* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.6.0.4266
+* Tools Package 2.2.0.2801
+* latest-v2.X 2.0.0.6211
+* personalities 3.0.0.0
+* udd 3.0.0.562
 *
 ********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
+* Copyright 2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -60,7 +62,7 @@ extern "C" {
 	#define WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	#define WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
+	#define WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@@ -87,64 +89,120 @@ extern "C" {
 	#define WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	#define WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
+	#define WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SW2 (P0_4)
+	#define CYBSP_USER_BTN1 CYBSP_SW2
+	#define CYBSP_USER_BTN CYBSP_SW2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_UART_RX (P5_0)
+	#define CYBSP_DEBUG_UART_RX CYBSP_UART_RX
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_UART_TX (P5_1)
+	#define CYBSP_DEBUG_UART_TX CYBSP_UART_TX
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_LED3 (P6_3)
+	#define CYBSP_USER_LED1 CYBSP_LED3
+	#define CYBSP_USER_LED CYBSP_LED3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_I2C_SCL (P6_4)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_I2C_SDA (P6_5)
+#endif //defined (CY_USING_HAL)
 #define SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_ENABLED SWDIO_ENABLED
 #define SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PORT SWDIO_PORT
 #define SWDIO_PORT_NUM 6U
+#define CYBSP_SWDIO_PORT_NUM SWDIO_PORT_NUM
 #define SWDIO_PIN 6U
+#define CYBSP_SWDIO_PIN SWDIO_PIN
 #define SWDIO_NUM 6U
+#define CYBSP_SWDIO_NUM SWDIO_NUM
 #define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_DRIVEMODE SWDIO_DRIVEMODE
 #define SWDIO_INIT_DRIVESTATE 1
+#define CYBSP_SWDIO_INIT_DRIVESTATE SWDIO_INIT_DRIVESTATE
 #ifndef ioss_0_port_6_pin_6_HSIOM
 	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
 #endif
 #define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_HSIOM SWDIO_HSIOM
 #define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWDIO_IRQ SWDIO_IRQ
 #if defined (CY_USING_HAL)
 	#define SWDIO_HAL_PORT_PIN P6_6
+	#define CYBSP_SWDIO_HAL_PORT_PIN SWDIO_HAL_PORT_PIN
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define SWDIO P6_6
+	#define CYBSP_SWDIO SWDIO
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+	#define CYBSP_SWDIO_HAL_IRQ SWDIO_HAL_IRQ
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	#define SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
+	#define SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+	#define CYBSP_SWDIO_HAL_DIR SWDIO_HAL_DIR
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+	#define CYBSP_SWDIO_HAL_DRIVEMODE SWDIO_HAL_DRIVEMODE
 #endif //defined (CY_USING_HAL)
 #define SWCLK_ENABLED 1U
+#define CYBSP_SWDCK_ENABLED SWCLK_ENABLED
 #define SWCLK_PORT GPIO_PRT6
+#define CYBSP_SWDCK_PORT SWCLK_PORT
 #define SWCLK_PORT_NUM 6U
+#define CYBSP_SWDCK_PORT_NUM SWCLK_PORT_NUM
 #define SWCLK_PIN 7U
+#define CYBSP_SWDCK_PIN SWCLK_PIN
 #define SWCLK_NUM 7U
+#define CYBSP_SWDCK_NUM SWCLK_NUM
 #define SWCLK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_DRIVEMODE SWCLK_DRIVEMODE
 #define SWCLK_INIT_DRIVESTATE 1
+#define CYBSP_SWDCK_INIT_DRIVESTATE SWCLK_INIT_DRIVESTATE
 #ifndef ioss_0_port_6_pin_7_HSIOM
 	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
 #endif
 #define SWCLK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWDCK_HSIOM SWCLK_HSIOM
 #define SWCLK_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWDCK_IRQ SWCLK_IRQ
 #if defined (CY_USING_HAL)
 	#define SWCLK_HAL_PORT_PIN P6_7
+	#define CYBSP_SWDCK_HAL_PORT_PIN SWCLK_HAL_PORT_PIN
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define SWCLK P6_7
+	#define CYBSP_SWDCK SWCLK
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define SWCLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+	#define CYBSP_SWDCK_HAL_IRQ SWCLK_HAL_IRQ
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	#define SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
+	#define SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+	#define CYBSP_SWDCK_HAL_DIR SWCLK_HAL_DIR
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define SWCLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+	#define CYBSP_SWDCK_HAL_DRIVEMODE SWCLK_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_LED4 (P7_1)
+	#define CYBSP_USER_LED2 CYBSP_LED4
 #endif //defined (CY_USING_HAL)
 
 extern const cy_stc_gpio_pin_config_t WCO_IN_config;
@@ -156,12 +214,16 @@ extern const cy_stc_gpio_pin_config_t WCO_OUT_config;
 	extern const cyhal_resource_inst_t WCO_OUT_obj;
 #endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t SWDIO_config;
+#define CYBSP_SWDIO_config SWDIO_config
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t SWDIO_obj;
+	#define CYBSP_SWDIO_obj SWDIO_obj
 #endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t SWCLK_config;
+#define CYBSP_SWDCK_config SWCLK_config
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t SWCLK_obj;
+	#define CYBSP_SWDCK_obj SWCLK_obj
 #endif //defined (CY_USING_HAL)
 
 void init_cycfg_pins(void);