CY8CPROTO-063-BLE BSP

Overview

The PSoC™ 6 BLE Prototyping Kit (CY8CPROTO-063-BLE) is a low-cost hardware platform that enables design and debug of PSoC™ 6 MCUs. This kit is designed with a snap-away form-factor, allowing users to separate the KitProg (on-board programmer and debugger) from the target board and use independently.

To use code from the BSP, simply include a reference to cybsp.h.

Features

Kit Features:

• BLE 5.0 certified CYBLE-416045-02 EZ-BLE module with onboard crystal oscillators, trace antenna, passive components and PSoC™ 63 MCU
• Up to 36 GPIOs in a 14x18.5x2 mm package
• Supports digital programmable logic, capacitive-sensing with CAPSENSE, a PDM-PCM digital microphone interface, a Quad-SPI interface, high-performance analog-to-digital converter (ADC), low-power comparators, and standard communication and timing peripherals.

Kit Contents:

• PSoC™ 6 BLE Prototyping Board
• USB Type-A to Micro-B cable
• Quick Start Guide

BSP Configuration

The BSP has a few hooks that allow its behavior to be configured. Some of these items are enabled by default while others must be explicitly enabled. Items enabled by default are specified in the CY8CPROTO-063-BLE.mk file. The items that are enabled can be changed by creating a custom BSP or by editing the application makefile.

Components:

• Device specific category reference (e.g.: CAT1) - This component, enabled by default, pulls in any device specific code for this board.

Defines:

• CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip if it has one.
• CY_USING_HAL - This define, enabled by default, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers.
• CYBSP_CUSTOM_SYSCLK_PM_CALLBACK - This define, disabled by default, causes the BSP to skip registering its default SysClk Power Management callback, if any, and instead to invoke the application-defined function cybsp_register_custom_sysclk_pm_callback to register an application-specific callback.

Clock Configuration

Clock	Source	Output Frequency
FLL	IMO	100.0 MHz
PLL	IMO	48.0 MHz
CLK_HF0	CLK_PATH0	100 MHz

Power Configuration

• System Active Power Mode: LP
• System Idle Power Mode: Deep Sleep
• VDDA Voltage: 3300 mV
• VDDD Voltage: 3300 mV

See the BSP Setttings for additional board specific configuration settings.

API Reference Manual

The CY8CPROTO-063-BLE Board Support Package provides a set of APIs to configure, initialize and use the board resources.

See the BSP API Reference Manual for the complete list of the provided interfaces.

More information

• CY8CPROTO-063-BLE BSP API Reference Manual
• CY8CPROTO-063-BLE Documentation
• Cypress Semiconductor, an Infineon Technologies Company
• Infineon GitHub
• ModusToolbox™

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© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2022.