Upload TARGET_CY8CPROTO-063-BLE 2.1.0.21729

Infineon · Apr 14, 2021 · 7e3993f · 7e3993f
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diff --git a/.cyignore b/.cyignore
@@ -0,0 +1 @@
+docs
diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
@@ -4,7 +4,7 @@
 * Description:
 * Wrapper function to initialize all generated code.
 * This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2801
+* Tools Package 2.2.0.2790
 * latest-v2.X 2.0.0.6211
 * personalities 3.0.0.0
 * udd 3.0.0.562

diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
@@ -4,7 +4,7 @@
 * Description:
 * Simple wrapper header containing all generated files.
 * This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2801
+* Tools Package 2.2.0.2790
 * latest-v2.X 2.0.0.6211
 * personalities 3.0.0.0
 * udd 3.0.0.562

diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
@@ -4,7 +4,7 @@
 * Description:
 * Sentinel file for determining if generated source is up to date.
 * This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2801
+* Tools Package 2.2.0.2790
 * latest-v2.X 2.0.0.6211
 * personalities 3.0.0.0
 * udd 3.0.0.562

diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
@@ -5,7 +5,7 @@
 * Contains warnings and errors that occurred while generating code for the
 * design.
 * This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2801
+* Tools Package 2.2.0.2790
 * latest-v2.X 2.0.0.6211
 * personalities 3.0.0.0
 * udd 3.0.0.562

diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
@@ -4,7 +4,7 @@
 * Description:
 * Peripheral Hardware Block configuration
 * This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2801
+* Tools Package 2.2.0.2790
 * latest-v2.X 2.0.0.6211
 * personalities 3.0.0.0
 * udd 3.0.0.562

diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
@@ -4,7 +4,7 @@
 * Description:
 * Peripheral Hardware Block configuration
 * This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2801
+* Tools Package 2.2.0.2790
 * latest-v2.X 2.0.0.6211
 * personalities 3.0.0.0
 * udd 3.0.0.562

diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
@@ -4,7 +4,7 @@
 * Description:
 * Pin configuration
 * This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2801
+* Tools Package 2.2.0.2790
 * latest-v2.X 2.0.0.6211
 * personalities 3.0.0.0
 * udd 3.0.0.562

diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
@@ -4,7 +4,7 @@
 * Description:
 * Pin configuration
 * This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2801
+* Tools Package 2.2.0.2790
 * latest-v2.X 2.0.0.6211
 * personalities 3.0.0.0
 * udd 3.0.0.562

diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
@@ -4,7 +4,7 @@
 * Description:
 * Establishes all necessary connections between hardware elements.
 * This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2801
+* Tools Package 2.2.0.2790
 * latest-v2.X 2.0.0.6211
 * personalities 3.0.0.0
 * udd 3.0.0.562

diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
@@ -4,7 +4,7 @@
 * Description:
 * System configuration
 * This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2801
+* Tools Package 2.2.0.2790
 * latest-v2.X 2.0.0.6211
 * personalities 3.0.0.0
 * udd 3.0.0.562

diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
@@ -4,7 +4,7 @@
 * Description:
 * System configuration
 * This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2801
+* Tools Package 2.2.0.2790
 * latest-v2.X 2.0.0.6211
 * personalities 3.0.0.0
 * udd 3.0.0.562

diff --git a/COMPONENT_BSP_DESIGN_MODUS/design.modus b/COMPONENT_BSP_DESIGN_MODUS/design.modus
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <Design version="12" xmlns="http://cypress.com/xsd/cydesignfile_v3">
-    <ToolInfo version="2.2.0.2801"/>
+    <ToolInfo version="2.2.0.2790"/>
     <Devices>
         <Device mpn="CYBLE-416045-02">
             <BlockConfig>

diff --git a/CY8CPROTO-063-BLE.mk b/CY8CPROTO-063-BLE.mk
@@ -6,7 +6,7 @@
 #
 ################################################################################
 # \copyright
-# Copyright 2018-2020 Cypress Semiconductor Corporation
+# Copyright 2018-2021 Cypress Semiconductor Corporation
 # SPDX-License-Identifier: Apache-2.0
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,11 +30,14 @@ endif
 include $(dir $(lastword $(MAKEFILE_LIST)))/locate_recipe.mk
 
 # MCU device selection
+#    Changing the device should be done using “make bsp” or “make update_bsp” with the “DEVICE_GEN”
+#    variable set to the new MCU. If you change the device manually here you must also update the
+#    design.modus file and re-run the device configurator.
 DEVICE:=CYBLE-416045-02
 # Default target core to CM4 if not already set
 CORE?=CM4
 # Basic architecture specific components
-COMPONENTS+=CAT1A
+COMPONENTS+=$(TARGET) CAT1 CAT1A
 
 ifeq ($(CORE),CM4)
 # Additional components supported by the target

diff --git a/README.md b/README.md
@@ -27,13 +27,13 @@ To use code from the BSP, simply include a reference to `cybsp.h`.
 The BSP has a few hooks that allow its behavior to be configured. Some of these items are enabled by default while others must be explicitly enabled. Items enabled by default are specified in the CY8CPROTO-063-BLE.mk file. The items that are enabled can be changed by creating a custom BSP or by editing the application makefile.
 
 Components:
-    * Device specific HAL reference (e.g.: PSOC6HAL) - This component, enabled by default, pulls in the version of the HAL that is applicable for this board.
-    * BSP_DESIGN_MODUS - This component, enabled by default, causes the Configurator generated code for this specific BSP to be included. This should not be used at the same time as the CUSTOM_DESIGN_MODUS component.
-    * CUSTOM_DESIGN_MODUS - This component, disabled by default, causes the Configurator generated code from the application to be included. This assumes that the application provides configurator generated code. This should not be used at the same time as the BSP_DESIGN_MODUS component.
+* Device specific category reference (e.g.: CAT1) - This component, enabled by default, pulls in any device specific code for this board.
+* BSP_DESIGN_MODUS - This component, enabled by default, causes the Configurator generated code for this specific BSP to be included. This should not be used at the same time as the CUSTOM_DESIGN_MODUS component.
+* CUSTOM_DESIGN_MODUS - This component, disabled by default, causes the Configurator generated code from the application to be included. This assumes that the application provides configurator generated code. This should not be used at the same time as the BSP_DESIGN_MODUS component.
 
 Defines:
-    * CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip.
-    * CY_USING_HAL - This define, enabled by default, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers.
+* CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip if it has one.
+* CY_USING_HAL - This define, enabled by default, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers.
 
 ### Clock Configuration
 
@@ -50,6 +50,8 @@ Defines:
 * VDDA Voltage: 3300 mV
 * VDDD Voltage: 3300 mV
 
+See the [BSP Setttings][settings] for additional board specific configuration settings.
+
 ## API Reference Manual
 
 The CY8CPROTO-063-BLE Board Support Package provides a set of APIs to configure, initialize and use the board resources.
@@ -64,6 +66,7 @@ See the [BSP API Reference Manual][api] for the complete list of the provided in
 * [ModusToolbox](https://www.cypress.com/products/modustoolbox-software-environment)
 
 [api]: https://cypresssemiconductorco.github.io/TARGET_CY8CPROTO-063-BLE/html/modules.html
+[settings]: https://cypresssemiconductorco.github.io/TARGET_CY8CPROTO-063-BLE/html/md_bsp_settings.html
 
 ---
-© Cypress Semiconductor Corporation, 2019-2020.
+© Cypress Semiconductor Corporation, 2019-2021.
diff --git a/RELEASE.md b/RELEASE.md
@@ -8,17 +8,24 @@ The CY8CPROTO-063-BLE library includes the following:
 * BSP specific makefile to configure the build process for the board
 * cybsp.c/h files to initialize the board and any system peripherals
 * cybsp_types.h file describing basic board setup
-* CM4 Linker script & startup code for GCC, IAR, ARM toolchains
-* CM0+ Linker script & startup code for GCC, IAR, ARM toolchains
+* CM4 Linker script & startup code for GCC, IAR, and ARM toolchains
+* CM0+ Linker script & startup code for GCC, IAR, and ARM toolchains
 * Configurator design files (and generated code) to setup board specific peripherals
 * .lib file references for all dependent libraries
 * API documentation
 
 ### What Changed?
+#### v2.1.0
+* Added component CAT1 to all boards
+* Added new components for connectivity chips
+* Added BT configuration settings for boards that support it
+* Minor documentation updates
+#### v2.0.1
+* Minor update to better handle when to include the SCL library in the build
 #### v2.0.0
 * Updated design files and GeneratedSource with ModusToolbox 2.2 release
 * Migrated pin definitions into design.modus file
-* Updated clock frequencies to 144 MHz (fast) / 72 MHz (slow)
+* Updated clock frequencies to 100 MHz (fast) / 50 MHz (slow)
 * Updated MPNs on some boards to non-obsolete parts
 * Switched psoc6pdl dependency to new mtb-pdl
 * Switched psoc6hal dependency to new mtb-hal
@@ -51,8 +58,8 @@ This version of the CY8CPROTO-063-BLE BSP was validated for compatibility with t
 
 | Software and Tools                        | Version |
 | :---                                      | :----:  |
-| ModusToolbox Software Environment         | 2.2     |
-| GCC Compiler                              | 9.2     |
+| ModusToolbox Software Environment         | 2.2.1   |
+| GCC Compiler                              | 9.3.1   |
 | IAR Compiler                              | 8.4     |
 | ARM Compiler                              | 6.11    |
 
@@ -68,4 +75,4 @@ Minimum required ModusToolbox Software Environment: v2.2
 [api]: modules.html
 
 ---
-© Cypress Semiconductor Corporation, 2019-2020.
+© Cypress Semiconductor Corporation, 2019-2021.
diff --git a/cybsp.c b/cybsp.c
@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2020 Cypress Semiconductor Corporation
+* Copyright 2018-2021 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -36,38 +36,44 @@
 extern "C" {
 #endif
 
-/* The sysclk deep sleep callback is recommended to be the last callback that
-* is executed before entry into deep sleep mode and the first one upon
-* exit the deep sleep mode.
-* Doing so minimizes the time spent on low power mode entry and exit.
-*/
+// The sysclk deep sleep callback is recommended to be the last callback that is executed before
+// entry into deep sleep mode and the first one upon exit the deep sleep mode.
+// Doing so minimizes the time spent on low power mode entry and exit.
 #ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
     #define CYBSP_SYSCLK_PM_CALLBACK_ORDER  (255u)
 #endif
 
 #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
 static cyhal_sdio_t sdio_obj;
 
+//--------------------------------------------------------------------------------------------------
+// cybsp_get_wifi_sdio_obj
+//--------------------------------------------------------------------------------------------------
 cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
 {
     return &sdio_obj;
 }
-#endif
 
-/**
- * Registers a power management callback that prepares the clock system
- * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep.
- * NOTE: This is called automatically as part of \ref cybsp_init
- */
+
+#endif // if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
+
+//--------------------------------------------------------------------------------------------------
+// cybsp_register_sysclk_pm_callback
+//
+// Registers a power management callback that prepares the clock system for entering deep sleep mode
+// and restore the clocks upon wakeup from deep sleep.
+// NOTE: This is called automatically as part of \ref cybsp_init
+//--------------------------------------------------------------------------------------------------
 static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
 {
-    cy_rslt_t result = CY_RSLT_SUCCESS;
-    static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL};
-    static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = {
-        .callback = &Cy_SysClk_DeepSleepCallback,
-        .type = CY_SYSPM_DEEPSLEEP,
+    cy_rslt_t                             result                         = CY_RSLT_SUCCESS;
+    static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL };
+    static cy_stc_syspm_callback_t        cybsp_sysclk_pm_callback       =
+    {
+        .callback       = &Cy_SysClk_DeepSleepCallback,
+        .type           = CY_SYSPM_DEEPSLEEP,
         .callbackParams = &cybsp_sysclk_pm_callback_param,
-        .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
+        .order          = CYBSP_SYSCLK_PM_CALLBACK_ORDER
     };
 
     if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
@@ -77,66 +83,69 @@ static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
     return result;
 }
 
+
+//--------------------------------------------------------------------------------------------------
+// cybsp_init
+//--------------------------------------------------------------------------------------------------
 cy_rslt_t cybsp_init(void)
 {
-    /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */
-#if defined(CY_USING_HAL)
+    // Setup hardware manager to track resource usage then initialize all system (clock/power) board
+    // configuration
+    #if defined(CY_USING_HAL)
     cy_rslt_t result = cyhal_hwmgr_init();
 
     if (CY_RSLT_SUCCESS == result)
     {
         result = cyhal_syspm_init();
     }
 
-#ifdef CY_CFG_PWR_VDDA_MV
-    if(CY_RSLT_SUCCESS == result)
+    #ifdef CY_CFG_PWR_VDDA_MV
+    if (CY_RSLT_SUCCESS == result)
     {
         cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV);
     }
-#endif
+    #endif
 
-#else
+    #else // if defined(CY_USING_HAL)
     cy_rslt_t result = CY_RSLT_SUCCESS;
-#endif
+    #endif // if defined(CY_USING_HAL)
 
-#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
+    #if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
     init_cycfg_all();
-#endif
+    #endif
 
     if (CY_RSLT_SUCCESS == result)
     {
         result = cybsp_register_sysclk_pm_callback();
     }
 
-#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
-    /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require
-     * specific peripheral instances.
-     * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
-     * done when starting up WiFi.
-     */
+    #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
+    // Initialize SDIO interface. This must be done before other HAL API calls as some SDIO
+    // implementations require specific peripheral instances.
+    // NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary().
+    // This is typically done when starting up WiFi.
     if (CY_RSLT_SUCCESS == result)
     {
-        /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
-         * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK.
-         */
+        // Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2,
+        // CYBSP_WIFI_SDIO_D3, CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK.
         result = cyhal_sdio_init(
-                &sdio_obj,
-                CYBSP_WIFI_SDIO_CMD,
-                CYBSP_WIFI_SDIO_CLK,
-                CYBSP_WIFI_SDIO_D0,
-                CYBSP_WIFI_SDIO_D1,
-                CYBSP_WIFI_SDIO_D2,
-                CYBSP_WIFI_SDIO_D3);
+            &sdio_obj,
+            CYBSP_WIFI_SDIO_CMD,
+            CYBSP_WIFI_SDIO_CLK,
+            CYBSP_WIFI_SDIO_D0,
+            CYBSP_WIFI_SDIO_D1,
+            CYBSP_WIFI_SDIO_D2,
+            CYBSP_WIFI_SDIO_D3);
     }
-#endif /* defined(CYBSP_WIFI_CAPABLE) */
+    #endif // defined(CYBSP_WIFI_CAPABLE)
 
-    /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by
-     * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
-     * (cyreservedresources.list) to make sure no resources are reserved by both.
-     */
+    // CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was
+    // reserved by user previously. Please review the Device Configurator (design.modus) and the BSP
+    // reservation list (cyreservedresources.list) to make sure no resources are reserved by both.
     return result;
 }
 
+
 #if defined(__cplusplus)
 }
 #endif