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This repository has been archived by the owner on Sep 2, 2023. It is now read-only.

Issues: mrisc32/mrisc32

17 Open 106 Closed
17 Open 106 Closed
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Issues list

Add a precise time counter system register
#147 opened Jun 29, 2023 by mbitsnbites
Refactor instruction formats (make way for more Format A instructions)
#146 opened May 5, 2023 by mbitsnbites v0.4
Add bit rotate instructions (ROR, ROL) investigate
#144 opened Apr 13, 2023 by mbitsnbites v0.4
Do we really need SNE & FSNE? investigate
#142 opened Sep 17, 2022 by mbitsnbites v0.4
Add LDM/STM (LoaD Multiple/STore Multiple) investigate
#141 opened Jun 28, 2022 by mbitsnbites v0.4
Add instructions for approximate floating-point reciprocals
#140 opened Mar 25, 2022 by mbitsnbites
Fix pseudo-code for all base arch instructions
#138 opened Jul 20, 2021 by mbitsnbites v0.4
Add I vs D cache coherence instructions
#125 opened Mar 19, 2021 by mbitsnbites
1
Add 32:32->32 division operations (where the lower 32 bits are zero) investigate
#111 opened Oct 21, 2020 by mbitsnbites
Add facilities for masked vector load/store
#108 opened Aug 28, 2020 by mbitsnbites
1
Add fused multiply-accumulate (FMA)
#107 opened Aug 25, 2020 by mbitsnbites
Idea for compressed instructions: Use a special 32-bit VLIW format
#103 opened Feb 20, 2020 by mbitsnbites
3
Define and implement an interrupt model
#88 opened Apr 11, 2019 by mbitsnbites
Float to int conversion: Clamp the result to the integer range
#79 opened Feb 20, 2019 by mbitsnbites
1
Add a "Register Length" tag to vector registers
#39 opened Jul 23, 2018 by mbitsnbites
Add a "get element" instruction for vector registers
#38 opened Jul 23, 2018 by mbitsnbites
Add a "get mask" instruction for vector registers
#37 opened Jul 22, 2018 by mbitsnbites
1
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