Add I vs D cache coherence instructions

[mbitsnbites]

A common method for synchronizing the I$ with recently updated D$ content (when loading program/patching code, JIT, etc) goes as follows:

1. Flush affected D$ lines (loop over memory range).
2. Wait for 1 to complete (take effect in next level memory).
3. Invalidate affected I$ lines (loop over memory range).
4. Wait for 3 to complete.
5. Flush the instruction pipeline.

To support this we need instructions for the following tasks (at least):

• Query the I & D cache line sizes.
• Flush a D cache line.
• Invalidate an I cache line.
• Instruction barrier (of different kinds).
• Data barrier (of different kinds).

Some inspiration from AArch64: https://github.com/tianocore/edk2/blob/master/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S

[mbitsnbites]

Currently implemented:

• SYNC - Combined instruction and data barrier
• CCTRL - Cache Control (invalidate, flush, ...)

Querying cache line sizes etc should be implemented via system registers (XCHGSR).