arch-x86: Fix TLB Assertion Error on CFLUSH

[Lukas-Zenick]

Fixed the assertion statement in the cpu's translation.hh file so that it doesn't fail the assertion if the cache is clean.

I compile this c code to test

#include <stdio.h>

static inline void clflush(volatile void *p) {
    __asm__ volatile ("clflush (%0)" : : "r"(p) : "memory");
}

int main() {
    int data = 42;  // Example variable

    printf("Value before clflush: %d\n", data);

    clflush(&data);

    printf("Value after clflush: %d\n", data);

    return 0;
}

And run it with this script
./build/X86/gem5.opt configs/learning_gem5/part1/two_level.py ./test
In order to verify that it no longer fails the assertion check.

GitHub Issue: #862
Change-Id: I6004662e7c99f637ba0ddb07d205d1657708e99f

[hnpl]

I still think we need to have the assertion mode == state->mode without the ||. However, I'm okay with this if it means this change allows clflush to work.

[powerjg]

I feel a little uncomfortable with this change. However, if it is what makes the most sense (e.g., this can't be fixed by changing the original Mode, then I'm good with this change.

Thanks for the contribution!

[hnpl]

Is there a plan to merge this to v24.0 release?