Chipyard 1.11.0 Release

Added

• Provide example of tethered-config simulation with MultiHarnessBinders (by @jerryz123 in #1484)
• Add release note automation (by @abejgonzalez in #1548)
• Improve peripheral config binders (Reapply #1511) (by @jerryz123 in #1527)
• UPF Generation (by @sriramsridhar23 in #1347)
• Improve: SiFive peripheral device doumentation (by @T-K-233 in #1578)
• Bump to latest rocket-chip | integrated fixed-point | pull in stage/phase (by @jerryz123 in #1577)
• Enable precommit | Format files (by @abejgonzalez in #1585)
• KLayout section of Sky130+OpenROAD tutorial (by @nayiri-k in #1514)
• Added useful "Build script exited at step X" errors for each step in build-setup.sh (by @JL102 in #1614)
• Adds support for Digilent Nexys Video FPGA board. (by @milovanovic in #1616)
• Add NarrowRocketCache config fragment (by @jerryz123 in #1603)
• Add Caliptra AES256 ECB engine as RoCC accelerator (by @abejgonzalez in #1642)
• Support using HarnessBinders without IOBinders (by @jerryz123 in #1636)
• Add Bringup on Arty100T config, using PMOD-gpio for ser-tl (by @jerryz123 in #1657)
• Install uart_tsi utility as part of build-toolchain-extra (by @jerryz123 in #1670)
• Add spike devices (by @joey0320 in #1692)
• Bump testchipip to support multi-serial-tl (by @jerryz123 in #1630)
• ADD: bump fpga-shell (by @T-K-233 in #1703)
• Add UART device/JTAG to Arty100T default design (by @jerryz123 in #1712)
• Add generators/ submodule status check to all Make targets (by @jerryz123 in #1718)
• Add clearer --skip flags to build-setup (by @jerryz123 in #1724)
• Add Baremetal IDE support (by @T-K-233 in #1534)
• ADD: add information on Baremetal-IDE in docs (by @T-K-233 in #1730)
• Support clustered-cores (by @jerryz123 in #1629)
• Add debug clock tap port to all default designs (by @jerryz123 in #1697)
• Add support for symmetric serial-tilelink (by @jerryz123 in #1716)
• Add Chip ID Pin and Port (by @schwarz-em in #1721)
• FastSimRocketConfig with no TLMonitors (by @joey0320 in #1752)
• Use lean conda for faster initial setup (by @joey0320 in #1750)
• Add BroadcastCoherence rocket config (by @jerryz123 in #1755)

Changed

• Bump FireMarshal (by @abejgonzalez in #1556)
• Bump spike | support M-mode only cosim (by @jerryz123 in #1530)
• Bump to chisel3.6 (by @jerryz123 in #1531)
• Replace Dromajo FireSim bridge with Cospike (by @abejgonzalez in #1588)
• Add PortAPI between IO and Harness blocks (by @jerryz123 in #1610)
• REFACTOR: change bootaddr register address and PC reset vector address (by @T-K-233 in #1605)
• REFACTOR: rename arty35t explicitly (by @T-K-233 in #1682)
• Add HasHarnessInstantiators into MultiHarnessBinder (by @abejgonzalez in #1674)
• Install CIRCT out of Conda (by @abejgonzalez in #1675)
• [cd] Bump CIRCT from firtool-1.58.0 to firtool-1.60.0 (copy #1688) (by @mergify[bot] in #1689)
• Bump constellation with improved TL-noc (by @jerryz123 in #1633)
• Update testchipip imports with new testchipip organization (by @jerryz123 in #1710)
• CHANGE: Set scratchpad as default config (by @T-K-233 in #1719)
• Rename blocks/cache submodules to match new chipsalliance ownership (by @jerryz123 in #1726)
• Rename timeout_cycles to TIMEOUT_CYCLES to match convention (by @jerryz123 in #1706)
• [cd] Bump CIRCT from firtool-1.60.0 to firtool-1.61.0 (copy #1691) (by @mergify[bot] in #1699)
• Bump tcip/barf/marshal/fsim (by @joey0320 in #1748)
• Remove skip-validate option (by @joey0320 in #1749)
• Add .gitignore for Embench Build Folder (by @vighneshiyer in #1754)
• Bump fsim (by @joey0320 in #1756)

Fixed

• Bump lockfiles | Force user-installed conda during conda-lock (by @abejgonzalez in #1555)
• Fix FIFO-fixing for PRCI bus (by @jerryz123 in #1563)
• Fix VCU118 freq adjustment configs (by @jerryz123 in #1597)
• Fix Arty100T verilog build (by @jerryz123 in #1608)
• Make scripts/insert-includes.py use Python from conda env (by @hansungk in #1615)
• Fix icenet-loopback clock and reset domain (by @joey0320 in #1612)
• Bump FireMarshal for linux rng init fix (by @raghav-g13 in #1620)
• Bump barstools (by @abejgonzalez in #1625)
• [vlsi][ci skip] Fix tutorial.mk so that INPUT_CONFS override only affects tutorials (by @jerryz123 in #1631)
• Fix regex for similar module names that are uniquified (by @abejgonzalez in #1640)
• Rebuild jars when sv/v files are changed + Add documentation on blackboxes (by @abejgonzalez in #1639)
• Use TARGET instead of PREFIX in /tests Makefile(s) (by @raghav-g13 in #1647)
• Fix IO direction for host Serial-TL port (by @ethanwu10 in #1654)
• More robust env.sh | Fix conda activate if in subshell (by @abejgonzalez in #1653)
• Always generate MFC Blackbox filelist (by @abejgonzalez in #1668)
• Remove references to ENABLE_YOSYS (by @abejgonzalez in #1695)
• FIX: fix vcu118 sd card frequency (by @T-K-233 in #1685)
• FIX: fix conda-lock version, >1.4.0 does not work! (by @T-K-233 in #1714)
• docs: correct to TOP_MACROCOMPILER_MODE (by @oharboe in #1744)
• Use non-lock-file conda requirements in RTD (by @abejgonzalez in #1742)
• Fix GCD MMIO example (by @jerryz123 in #1753)

Removed

• Remove pre-commit from env.sh (by @abejgonzalez in #1587)
• Remove Dromajo (by @abejgonzalez in #1598)
• Remove MultiClockHarnessAXIMem (by @jerryz123 in #1601)

Uncategorized

• Documentation: Change "don't use Windows" to "if using Windows, use WSL" (by @JL102 in #1572)
• docs: Add info on chipyard's tests directory and how to do multithreading in RTL simulations (by @JL102 in #1646)
• Reduce CDE lookups for IOBinders (by @tymcauley in #1720)
• Update deprecated APIs to prepare for Chisel 5 (by @tymcauley in #1723)
• Allow sed override in uniquify-module-names.py (by @tymcauley in #1729)
• Update deprecated/unused Chisel APIs (by @tymcauley in #1743)

Full Changelog: 1.10.0...1.11.0