Chipyard 1.11.0 Release

Added

• Provide example of tethered-config simulation with MultiHarnessBinders (by @jerryz123 in #1484)
• Add release note automation (by @abejgonzalez in #1548)
• Improve peripheral config binders (Reapply #1511) (by @jerryz123 in #1527)
• UPF Generation (by @sriramsridhar23 in #1347)
• Improve: SiFive peripheral device doumentation (by @T-K-233 in #1578)
• Bump to latest rocket-chip | integrated fixed-point | pull in stage/phase (by @jerryz123 in #1577)
• Enable precommit | Format files (by @abejgonzalez in #1585)
• KLayout section of Sky130+OpenROAD tutorial (by @nayiri-k in #1514)
• Added useful "Build script exited at step X" errors for each step in build-setup.sh (by @JL102 in #1614)
• Adds support for Digilent Nexys Video FPGA board. (by @milovanovic in #1616)
• Add NarrowRocketCache config fragment (by @jerryz123 in #1603)
• Add Caliptra AES256 ECB engine as RoCC accelerator (by @abejgonzalez in #1642)
• Support using HarnessBinders without IOBinders (by @jerryz123 in #1636)
• Add Bringup on Arty100T config, using PMOD-gpio for ser-tl (by @jerryz123 in #1657)
• Install uart_tsi utility as part of build-toolchain-extra (by @jerryz123 in #1670)
• Add spike devices (by @joey0320 in #1692)
• Bump testchipip to support multi-serial-tl (by @jerryz123 in #1630)
• ADD: bump fpga-shell (by @T-K-233 in #1703)
• Add UART device/JTAG to Arty100T default design (by @jerryz123 in #1712)
• Add generators/ submodule status check to all Make targets (by @jerryz123 in #1718)
• Add clearer --skip flags to build-setup (by @jerryz123 in #1724)
• Add Baremetal IDE support (by @T-K-233 in #1534)
• ADD: add information on Baremetal-IDE in docs (by @T-K-233 in #1730)
• Support clustered-cores (by @jerryz123 in #1629)
• Add debug clock tap port to all default designs (by @jerryz123 in #1697)
• Add support for symmetric serial-tilelink (by @jerryz123 in #1716)
• Add Chip ID Pin and Port (by @schwarz-em in #1721)
• FastSimRocketConfig with no TLMonitors (by @joey0320 in #1752)
• Use lean conda for faster initial setup (by @joey0320 in #1750)
• Add BroadcastCoherence rocket config (by @jerryz123 in #1755)

Changed

• Bump FireMarshal (by @abejgonzalez in #1556)
• Bump spike | support M-mode only cosim (by @jerryz123 in #1530)
• Bump to chisel3.6 (by @jerryz123 in #1531)
• Replace Dromajo FireSim bridge with Cospike (by @abejgonzalez in #1588)
• Add PortAPI between IO and Harness blocks (by @jerryz123 in #1610)
• REFACTOR: change bootaddr register address and PC reset vector address (by @T-K-233 in #1605)
• REFACTOR: rename arty35t explicitly (by @T-K-233 in #1682)
• Add HasHarnessInstantiators into MultiHarnessBinder (by @abejgonzalez in #1674)
• Install CIRCT out of Conda (by @abejgonzalez in #1675)
• [cd] Bump CIRCT from firtool-1.58.0 to firtool-1.60.0 (copy #1688) (by @mergify[bot] in #1689)
• Bump constellation with improved TL-noc (by @jerryz123 in #1633)
• Update testchipip imports with new testchipip organization (by @jerryz123 in #1710)
• CHANGE: Set scratchpad as default config (by @T-K-233 in #1719)
• Rename blocks/cache submodules to match new chipsalliance ownership (by @jerryz123 in #1726)
• Rename timeout_cycles to TIMEOUT_CYCLES to match convention (by @jerryz123 in #1706)
• [cd] Bump CIRCT from firtool-1.60.0 to firtool-1.61.0 (copy #1691) (by @mergify[bot] in #1699)
• Bump tcip/barf/marshal/fsim (by @joey0320 in #1748)
• Remove skip-validate option (by @joey0320 in #1749)
• Add .gitignore for Embench Build Folder (by @vighneshiyer in #1754)
• Bump fsim (by @joey0320 in #1756)

Fixed

• Bump lockfiles | Force user-installed conda during conda-lock (by @abejgonzalez in #1555)
• Fix FIFO-fixing for PRCI bus (by @jerryz123 in #1563)
• Fix VCU118 freq adjustment configs (by @jerryz123 in #1597)
• Fix Arty100T verilog build (by @jerryz123 in #1608)
• Make scripts/insert-includes.py use Python from conda env (by @hansungk in #1615)
• Fix icenet-loopback clock and reset domain (by @joey0320 in #1612)
• Bump FireMarshal for linux rng init fix (by @raghav-g13 in #1620)
• Bump barstools (by @abejgonzalez in #1625)
• [vlsi][ci skip] Fix tutorial.mk so that INPUT_CONFS override only affects tutorials (by @jerryz123 in #1631)
• Fix regex for similar module names that are uniquified (by @abejgonzalez in #1640)
• Rebuild jars when sv/v files are changed + Add documentation on blackboxes (by @abejgonzalez in #1639)
• Use TARGET instead of PREFIX in /tests Makefile(s) (by @raghav-g13 in #1647)
• Fix IO direction for host Serial-TL port (by @ethanwu10 in #1654)
• More robust env.sh | Fix conda activate if in subshell (by @abejgonzalez in #1653)
• Always generate MFC Blackbox filelist (by @abejgonzalez in #1668)
• Remove references to ENABLE_YOSYS (by @abejgonzalez in #1695)
• FIX: fix vcu118 sd card frequency (by @T-K-233 in #1685)
• FIX: fix conda-lock version, >1.4.0 does not work! (by @T-K-233 in #1714)
• docs: correct to TOP_MACROCOMPILER_MODE (by @oharboe in #1744)
• Use non-lock-file conda requirements in RTD (by @abejgonzalez in #1742)
• Fix GCD MMIO example (by @jerryz123 in #1753)

Removed

• Remove pre-commit from env.sh (by @abejgonzalez in #1587)
• Remove Dromajo (by @abejgonzalez in #1598)
• Remove MultiClockHarnessAXIMem (by @jerryz123 in #1601)

Uncategorized

• Documentation: Change "don't use Windows" to "if using Windows, use WSL" (by @JL102 in #1572)
• docs: Add info on chipyard's tests directory and how to do multithreading in RTL simulations (by @JL102 in #1646)
• Reduce CDE lookups for IOBinders (by @tymcauley in #1720)
• Update deprecated APIs to prepare for Chisel 5 (by @tymcauley in #1723)
• Allow sed override in uniquify-module-names.py (by @tymcauley in #1729)
• Update deprecated/unused Chisel APIs (by @tymcauley in #1743)

Full Changelog: 1.10.0...1.11.0

Chipyard 1.10.0 Release

Adds superscalar in-order core, prefetchers, architectural checkpointing, examples for custom-chiptop/tapeout-chip/flat-chiptop. FireSim bumped with new local FPGA support: Xilinx VCU118 (w/XDMA), Xilinx Alveo U250/U280 (w/XDMA, in addition to previous Vitis support), RHSResearch NiteFury II (w/XDMA). FireSim now also supports Xcelium for metasims.

Added

• QoL improvement to IOBinders + custom ChipTop example by @jerryz123 in #1399
• New Scala-based Config Finder by @abejgonzalez in #1424
• ADD: improve Makefile in tests/, add explicit arch flags by @T-K-233 in #1439
• Add mt-helloworld example by @jerryz123 in #1428
• Add tutorial software by @abejgonzalez in #1447
• Support not instantiating the TileClockGater/ResetSetter PRCI control by @jerryz123 in #1459
• ELF-based-loadmem | architectural restartable checkpoints by @jerryz123 in #1438
• Add embench build support by @jerryz123 in #1479
• Support multi-run of binaries by @jerryz123 in #1480
• Integrate barf (prefetchers) by @jerryz123 in #1505
• Add higher level explanations of RoCC + more resources by @nikhiljha in #1486
• Support banked/partitioned scratchpads by @jerryz123 in #1431
• Add dual-issue in-order "shuttle" core by @jerryz123 in #1495
• Improve peripheral fragments to include more peripheral devices and support instantiating multiple instances of same device by @T-K-233 in #1511

Changed

• Bump to latest rocket-chip/chisel3.5.6 by @jerryz123 in #1411
• Resolve merge conflicts in chisel3.5.6 bump by @jerryz123 in #1430
• PLL integration example + FlatChipTop/TestHarness by @jerryz123 in #1427
• bump testchipip by @joey0320 in #1434
• Fix ChipLikeQuadRocketConfig crossing by @jerryz123 in #1436
• Bump TestChipIp to improve default serial_tl behavior by @jerryz123 in #1435
• Bump testchipip to standardize TL serdesser bundle params by @jerryz123 in #1446
• Bump to Hammer 1.1.1 by @harrisonliew in #1451
• Always initialize fpga-shells with init-submodules.sh by @jerryz123 in #1456
• Support uni-directional TLSerdesser by @jerryz123 in #1476
• Move xcelium.mk out of top-level by @jerryz123 in #1482
• Set default config back to 1-channel by @jerryz123 in #1483
• Unify supernode/harness-clocking across chipyard/firesim/fpga by @jerryz123 in #1474
• Use fat jar's to remove SBT invocations by @abejgonzalez in #1375
• Bump to latest rocket-chip by @jerryz123 in #1475
• Improvements to chipyard clocking by @jerryz123 in #1489
• Downgrade cryptography | Pin linux sysroot by @abejgonzalez in #1494
• bump mempress by @joey0320 in #1498
• bump sha3 by @joey0320 in #1499
• Bump FireMarshal by @abejgonzalez in #1502
• Split NVDLA config out of ManyMMIOAccels config to reduce CI load by @jerryz123 in #1503
• Ignore barstools compilation if not needed by @abejgonzalez in #1504
• Disable NVDLA simulations in CI by @jerryz123 in #1507
• Update NoC example config to match new PRCI organization by @jerryz123 in #1509
• Bump gemmini by @jerryz123 in #1519

Fixed

• Various improvements and fixes by @jerryz123 in #1420
• Ensure conda cleanup regex properly filters out non-numeric chars by @abejgonzalez in #1425
• Clear screen on prompt by @abejgonzalez in #1449
• misc: many fixes to cospike by @tianrui-wei in #1450
• Uniquify module names that are common to Top & Model by @joey0320 in #1442
• Use pk/encoding.h for hello/mt-hello by @jerryz123 in #1454
• Fix no-uart configs by @jerryz123 in #1457
• Fix support for no-bootROM systems by @jerryz123 in #1458
• Check that HarnessClockInstantiator doesn't receive requests for similarly-named-clocks with different frequencies by @jerryz123 in #1460
• uniquify module names by @joey0320 in #1452
• Flip serial_tl_clock to be generated off-chip by @jerryz123 in #1445
• Move TestHarness to chipyard.harness, make chipyard/harness directory by @jerryz123 in #1463
• Separate out conda-lock generation into new script by @abejgonzalez in #1466
• Bump DRAMSim2 to avoid verbose log files by @jerryz123 in #1468
• Bump Verilator and use TestDriver.v as top by @abejgonzalez in #1398
• Add 1GB / 4GB DRAM firechip configs for FireSim VCU118 by @sagark in #1471
• Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness by @jerryz123 in #1465
• Make BootAddrReg optional by @jerryz123 in #1464
• Fix vcd/fst/fsdb waveform generation by @jerryz123 in #1473
• Switch RTL sims to absolute clock-generators by @jerryz123 in #1472
• Generate objdump | check BINARY | cospike fixes by @jerryz123 in #1467
• Small QOL fixes for Xcelium by @abejgonzalez in #1485
• (VCU118 DDR HarnessBinder)Fix data field width mismatch between DDR AXI and TileLink MemoryBus by @jerryhethatday in #1487
• Force conda-lock to v1 by @abejgonzalez in #1492
• Loosen/tighten conda requirements | Fix conda-lock req by @abejgonzalez in #1497
• Misc Makefile Fixes by @abejgonzalez in #1496
• Bump constellation to fix interconnect FIFO-fixers by @jerryz123 in #1510
• [ci skip] Fix broken docs link by @jerryz123 in #1515
• Revert changes to peripheral fragments by @jerryz123 in #1518

New Contributors

• @tianrui-wei made their first contribution in #1450
• @jerryhethatday made their first contribution in #1487
• @nikhiljha made their first contribution in #1486

Chipyard 1.9.1

This release fixes several bugs introduced with the 1.9.0 release.

What's Changed

• Various improvements and fixes by @jerryz123 in #1420
• Ensure conda cleanup regex properly filters out non-numeric chars by @abejgonzalez in #1425
• QoL improvement to IOBinders + custom ChipTop example by @jerryz123 in #1399
• New Scala-based Config Finder by @abejgonzalez in #1424
• Bump to latest rocket-chip/chisel3.5.6 by @jerryz123 in #1411
• Resolve merge conflicts in chisel3.5.6 bump by @jerryz123 in #1430
• PLL integration example + FlatChipTop/TestHarness by @jerryz123 in #1427
• bump testchipip by @joey0320 in #1434
• ADD: improve Makefile in tests/, add explicit arch flags by @T-K-233 in #1439
• Fix ChipLikeQuadRocketConfig crossing by @jerryz123 in #1436
• Bump TestChipIp to improve default serial_tl behavior by @jerryz123 in #1435
• Bump testchipip to standardize TL serdesser bundle params by @jerryz123 in #1446
• Add mt-helloworld example by @jerryz123 in #1428
• Clear screen on prompt by @abejgonzalez in #1449
• Add tutorial software by @abejgonzalez in #1447
• Bump to Hammer 1.1.1 by @harrisonliew in #1451
• Uniquify module names that are common to Top & Model by @joey0320 in #1442
• Use pk/encoding.h for hello/mt-hello by @jerryz123 in #1454
• Fix no-uart configs by @jerryz123 in #1457
• Fix support for no-bootROM systems by @jerryz123 in #1458
• Support not instantiating the TileClockGater/ResetSetter PRCI control by @jerryz123 in #1459
• Check that HarnessClockInstantiator doesn't receive requests for similarly-named-clocks with different frequencies by @jerryz123 in #1460
• uniquify module names by @joey0320 in #1452

Full Changelog: 1.9.0...1.9.1

Chipyard 1.9.0

Faster FIRRTL builds support with CIRCT. New software support for RISC-V GCC12 and Linux 6.2. Various bumps and fixes of all submodules.

Added

• Add example ring-only NoC Config by @jerryz123 in #1325
• Bump Gemmini by @hngenc, @jerryz123 in #1276 #1326
• Bump FireMarshal, Bump to newer RV toolchain (deprecate use of esp-tools for Gemmini) by @abejgonzalez, @jerryz123 in #1284 #1304 #1306 #1327 #1334 #1335 #1344 #1394 #1403 #1415
• Add support for VC707 FPGA board by @Lorilandly in #1278
• Fail simulations on TSI errors by @tymcauley in #1288
• Add pre-commit support by @abejgonzalez in #1294 #1310
• Bump mempress by @joey0320 in #1305
• CIRCT Integration by @abejgonzalez, @joey0320 in #1239 #1312 #1372 #1396
• Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip by @jerryz123 in #1303
• Spike-as-a-Tile and use for co-simulation by @jerryz123 in #1307 #1323 #1360
• Add clone-tile configs by @jerryz123 in #1322
• New Hammer by @harrisonliew in #1324 #1368 #1374 #1369 #1410
• Config finder make target by @abejgonzalez in #1328 #1381
• Arty100T board + TSI-over-UART by @jerryz123 in #1345
• Add graphml visualization section to docs by @schwarz-em in #1387
• Add a frag./config for MMIO only FireSim bridges by @abejgonzalez in #1393
• Add log of chisel elaboration to generated src by @jerryz123 in #1400
• Xcelium support by @sagark in #1386
• Bump Sodor @a0u in #1338
• Bump Constellation by @jerryz123 in #1339

Changed

• remove RocketTilesKey by @SingularityKChen in #1264
• Move setup script to scripts/, use a symlink at top-level by @jerryz123 in #1271
• Decoupled sbus width from boom|hwacha|gemmini memory interface widths by @jerryz123 in #1273
• Remove conda from build-toolchains-extra.sh by @abejgonzalez in #1266
• Rework build-setup | Add single-node CI by @abejgonzalez in #1282
• Switch simulators to C++17. by @jerryz123 in #1285
• Init FPGA submodules in build-setup.sh by @abejgonzalez in #1292
• Stripped down rocket configs for FireSim testing by @t14916 in #1302
• Add more minimal firesim configs for testing by @t14916 in #1313
• Add workshop info to README.md by @sagark in #1314
• Removed FireSim tests and harnesses by @nandor in #1317
• Move boom's tracegen interface to boom submodule by @jerryz123 in #1331
• Split up RocketConfigs.scala by @jerryz123 in #1340
• Sky130/Openroad Tutorial Fixes by @nayiri-k in #1392
• Testing VLSI commands for chipyard tutorial by @nayiri-k in #1395
• Reduce test cases for noc-config in CI by @jerryz123 in #1359
• Remove TLHelper, directly use tilelink node constructors by @jerryz123 in #1358
• Remove chisel-testers submodule by @abejgonzalez in #1378
• Cache .ivy2 and .sbt within Chipyard root directory by @abejgonzalez in #1362

Fixed

• Remove extra parenthesis by @odxa20 in #1261
• Fixed typo in Initial-Repo-Setup.rst by @PisonJay in #1269
• fix: S-interpolator for assert, assume and printf by @SingularityKChen in #1242
• Revert "fix: S-interpolator for assert, assume and printf" by @jerryz123 in #1272
• changelog: fixed TinyRocketArtyConfig FPGA reset signal polarity (Please Backport) by @T-K-233 in #1257
• Fix CY logo in README by @abejgonzalez in #1295
• More files to gitignore by @abejgonzalez in #1297
• Bump rocket-dsp-utils for ShiftRegisterMem fix. by @milovanovic in #1298
• Set VLOGMODEL=MODEL by default in variables.mk by @jerryz123 in #1337
• Fix compile breaking due to merge conflict by @jerryz123 in #1321
• Makefile bug fixes by @abejgonzalez in #1336
• Fix Verilog Prerequisites + Ignore mv stdout by @abejgonzalez in #1406
• Fix Chisel hierarchy API - Fixes #1356 by @abejgonzalez in #1361
• Remove gen-collateral when rebuilding by @joey0320 in #1342
• Fix VLSI input files list emission to avoid bash "too many arguments" error by @sagark in #1348
• Small build system improvements by @abejgonzalez in #1349
• Fix socket name length issues on CI by @jerryz123 in #1353
• Fix TestDriver.v missing from gen-collateral after recompiling by @joey0320 in #1354
• Consolidate CI testing configs to improve CI runtime by @jerryz123 in #1352
• Remove Duplicate Compiler Flags by @joey0320 in #1351
• fpga makefile clean fix by @joey0320 in #1357
• Fix newline in message in build-setup.sh by @jerryz123 in #1365
• Update assert message if configs can't be split by : by @abejgonzalez in #1373
• Remove Duplicate Compiler Flags by @joey0320 in #1367
• Move more tmp/ folders to a unique location by @abejgonzalez in #1382
• Remove stale conda env's after 2 days by @abejgonzalez in #1389
• Match CY/FireSim deps | Unpin deps | Update lockfiles by @abejgonzalez in #1391
• Only support HTML docs by @abejgonzalez in #1401
• Only HTML docs v2 by @abejgonzalez in #1402
• Fix ANSI color output by @jerryz123 in #1407
• Fix chisel elab errors not causing flow to stop by @jerryz123 in #1409
• lean gemmini tutorial by @sagark in #1413

Chipyard 1.8.1

Various fixes and improvements, bump FireSim to 1.15.1.

Added

• Bump chipyard to integrate mempress #1253

Changed

• Default VCS simulators should generate FSDB #1252
• Bump to FireSim 1.15.1 for various improvements #1258

Fixed

• Revert to using sbt-launch.jar to run SBT #1251
• Fix open files issue automatically on systems with a sufficiently large hard limit, to work around buildroot bug. #1258
• Fixed PATH issues in generated env.sh #1258
• Fixed scripts/repo-clean.sh to restore clean repo state again #1258

Chipyard 1.8.0

Adds support for NoC-based interconnects with Constellation (https://constellation.readthedocs.io/en/latest/). Switch to Conda for dependency/environment management. Bump Rocket Chip and other hardware libraries. Bump to FireSim 1.15.0.

Added

• RTL: Support for packet-switched NoC-based TileLink main bus interconnects with Constellation by @jerryz123 in #1224
• Conda: Support setting up a Chipyard development environment through Conda by @abejgonzalez in #1163
• Hammer: Fully open-source Sky130 flow tutorials in open-source and commercial tools by @nayiri-k in #1226
• Hammer: IR key history by @bdngo in #1226
• Hammer: Joules power analysis support by @dpgrubb13 in #1226
• Hammer: Tempus STA support by @harrisonliew in #1226

Changed

• RTL: Default memory-mapped addresses for fft/dsp/example MMIO accelerators changed to be non-overlapping by @jerryz123 in #1224
• Repo: Update SiFive submodules to new chipsalliance upstreams by @michael-etzkorn in #1208
• Rocketchip: Bumped to 1.6 by @jerryz123 in #1216
• Chisel: Bumped to 3.5.2 by @jerryz123 in #1216
• Firesim: Bumped to 1.15.0 by @jerryz123 #1224
• Firemarshal: Bumped to latest by @abejgonzalez in #1216

Fixed

• RTL: Fix clock frequency rounding by @sant0s12 in #1201
• Hammer: VCS FGP is now opt-in by @harrisonliew in #1226
• Dromajo: Fix to variable definition by @jzhou1318 in #1197
• Testchipip: Fix write-strobe handling for 64B configurations by @davidbiancolin in #1214
• Build: Ignore dotfiles in lookup_srcs by @jerryz123 in #1218

Chipyard 1.7.1

FireSim bump for new builddriver command and various fixes. See FireSim 1.14.1 CHANGELOG.md.

Changed

• Bump FireSim to 1.14.1

Chipyard 1.7.0

FireSim bump for local (on-premises) FPGA and distributed metasimulation support. Hammer now supports the OpenROAD open-source EDA tools for a fully open-source RTL-to-GDS VLSI flow.

Added

• Add a FireSim config with no mem port (#1172)
• Hammer OpenROAD plugins: Yosys (syn), OpenROAD (par), Magic (drc), Netgen (lvs) (#1183)

Changed

• Bump FireSim to 1.14.0
• Give the PRCI widgets valnames to clean up module naming (#1152)

Fixed

• Add missing Apache commons dependencies (fixes #1144) (#1147)
• Disable Boost for spike (#1168)
• VCS enhancements (#1150)
  • Support multi-thread VCS simv option like FGP, Xprof etc.
  • Idle tsi in the target thread
• Don't shallow clone submodules (revert #1064) (#1143)
• Remove extra spaces in FPGA makefile (#1135)

Chipyard 1.6.2

Minor fixes to FireSim.

Fixed

• Bump to FireSim 1.13.3 (#1134)

Chipyard 1.6.1

Minor fixes to FireSim.

Fixed

• Bump to FireSim 1.13.2 (#1133)