This respositort contains all vhdl codes and simulations of final year vlsi lab of NIT Rourkela
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Updated
Nov 15, 2016 - VHDL
This respositort contains all vhdl codes and simulations of final year vlsi lab of NIT Rourkela
This is a vlsi design of a hamming distance calculator circuit.
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
Cmos design of 16 bit adder 8bit full adder + 8 bit cla adder
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
Contains all the necessary lab tasks (Cadence Virtuoso) for ECE3002 VLSI System Design (VIT).
This repo contains golden vector and randomization testbenches for SRAM module.
The reference design of EE113's final project (Digital integrated Circuit design Fall 2020) at ShanghaiTech University
Codes performed in labs using Xilinx ISE 14.7
BRACU CSE460 Lab (Summer 2020)
A simple tool to demonstrate the physical design steps of VLSI Design Flow.
Domain Specific Hardware Accelerators - VLSI CAD Project
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
NGspice netlist files for simulation of analog and digital circuits.
Microshift Compression: An Efficient Image Compression Algorithm for Hardware
Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift re…
A full adder circuit is central to most digital circuits that perform addition or subtraction. It is so called because it adds together two binary digits, plus a carry-in digit to produce a sum and carry-out digit.1 It therefore has three inputs and two outputs.
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