vitis
Here are 85 public repositories matching this topic...
Vitis In-Depth Tutorials
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May 21, 2024 - C
A TFTP server running on Zynq-7000
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May 15, 2024 - C
VNx: Vitis Network Examples
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Apr 27, 2024 - Jupyter Notebook
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
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Apr 23, 2024 - C++
example of using iio to stream data from AD9361 with a coax cable loopback
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Apr 14, 2024 - C
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
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Apr 13, 2024 - VHDL
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
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Apr 13, 2024 - VHDL
Docker container containing the Vitis 2023.2 tools & PetaLinux
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Apr 8, 2024 - Dockerfile
Efficient Algorithm Level Error Detection for Number-Theoretic Transform
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Mar 2, 2024 - Python
Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)
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Feb 17, 2024 - C++
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