Skip to content
#

vitis

Star

Here are 85 public repositories matching this topic...

Language: All
Filter by language
All 85 C++ 20 C 18 VHDL 16 Tcl 11 Jupyter Notebook 4 Python 2 Scala 2 Shell 2 SystemVerilog 2 CMake 1
Sort: Fewest forks
Sort options
Most stars Fewest stars Most forks Fewest forks Recently updated Least recently updated

Florin623 / AXI-Lite-Slave-FFT-IP

Star 0

3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.

design communication-protocol pipeline digital hardware electronics signal-processing processor master-slave verilog fft vivado intellectual-property c-programming integrated-circuits microblaze axi interconnect microelectronics vitis
  • Updated Apr 13, 2024
  • VHDL

aryan-programmer / axi_stream_array_sum_microblaze

Star 1

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado microblaze axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls
  • Updated Dec 3, 2023
  • C

Improve this page

Add a description, image, and links to the vitis topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the vitis topic, visit your repo's landing page and select "manage topics."

Learn more