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Tranditional convolution implementation and verification in Verilog from scratch.
Updated
May 28, 2023
Verilog
Updated
May 5, 2023
Verilog
4-bit Von Neumann Microprocessor in FPGA
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Mar 18, 2023
HTML
Implementation of the ps2 protocol for the keyboard, where the device is a keyboard with a ps2 serial port, and the host is an Altera Cyclone® V FPGA board.
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Mar 29, 2023
Shell
🍟 Logic Design Verilog practice
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Apr 29, 2023
Verilog
Mathematical calculations on matrices in Verilog
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Jul 5, 2022
Verilog
A collection of code from CDA 4240C: Design of Digital System and Lab
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May 26, 2023
VHDL
CSE-2112 Digital Syatem Design LAb
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Jan 20, 2023
Verilog
Updated
Mar 14, 2023
Verilog
8-Digit LED Display driver for FPGA
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Jun 14, 2023
Verilog
experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga cmod s7 from digilent
Updated
Oct 24, 2023
Verilog
Verilog implementation of a computer architecture project (single-bus processor) on an iCEstick FPGA
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Aug 6, 2023
Verilog
UART_TX Implementation Using Verilog
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Nov 11, 2022
Verilog
experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent
Updated
May 29, 2023
Verilog
This is the repo for keeping track of all my FPGA learning activities.
Few Verilog Programs I had wrote for EC-220 Computer System Architecture
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Jun 20, 2023
Verilog
Updated
Dec 30, 2022
SystemVerilog
Pipelined processor design for RISC-V ISA
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May 5, 2023
Verilog
Implementation of UART serial communication on Virtex 6 FPGA
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Jun 9, 2023
Verilog
Use Verilog/VHDL and the ZYNQ board from Xilinx configure a wide range of logic circuits and use I/O devices build a wider array of circuit.
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