verilog-project

Here are 194 public repositories matching this topic...

Sumit0976 / Schoolbook-Multiplications

This project is done in Vivado in Verilog with hardware implementation and the project is optimized Schoolbook multiplier which is much faster than the traditional ones

optimization-algorithms verilog-project verilog-code

Updated Dec 16, 2023
Verilog

lakki0704 / Verilog_Project

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Verilog Projects : 1) Vending Machine 2)Traffic Light Controller

verilog-project

Updated Jun 30, 2023
SystemVerilog

jash0803 / Simple_Elevator_Design

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During the EL-203 course, we had to make a elevator controller project under Professor Biswajit Mishra.

state-diagram verilog-project fpga-programming

Updated Apr 24, 2024
Verilog

AsgharAZ / DDS-FIR-Low-Pass-Filter

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Exploring both MATLAB and Vivado Verilog in designing a Direct Digital Synthesizer (DDS) system with a FIR low-pass filter. This project goes into digital system design, signal processing, and hardware implementation.

fpga matlab verilog digital-signal-processing verilog-hdl low-pass-filter direct-digital-synthesizer verilog-project fpga-programming phase-accumulator sine-wave-generator

Updated May 26, 2024
Verilog

J0vial / 4-ALU-logic-Operation

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quartus verilog-project

Updated May 11, 2023

Keyan5 / intelunnati_adventurer

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Finite State Machine (FSM) designed to handle the movements of a Land Rover based on binary inputs. The FSM utilizes D flip-flops and combinatorial logic to transition between states and produce appropriate output signals for controlling the Land Rover's movement.

fsm verilog finite-state-machine verilog-hdl verilog-project verilog-code design-and-functional-simulation functional-simulation-of-land-rover-figo-fsm

Updated Jul 13, 2023
Verilog

Rudra-Joshi-002 / Verilog_Codes

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This Repository shows the implementation and results of various codes that I write in Verilog HDL

verilog verilog-hdl verilog-programs verilog-simulator verilog-project verilog-code

Updated May 17, 2024
Verilog

Sumit0976 / -Karatsuba-Algorithm

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2-Term Karatsuba and 3-Term Karatsuba Algorithm on FPGAs in Vivado using Verilog with diffrent bits and with 3 diffrent method.

verilog-project verilog-code hardware-implemenation

Updated Dec 16, 2023

salzhang / Booth-Multiplier

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rtl wallace-tree-multiplier multiplier verilog-project booth-multiplier

Updated Apr 3, 2024
Verilog

LeoCourbassier / CoreBassier

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RISC processor done in verilog hdl for FPGA

processor-architecture risc-processor verilog-project

Updated Jul 13, 2018
VHDL

mpdg837 / BilberryPI

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Projekt zintegorwanego chipu wykonanego Verilog HDL, będącego SOC na którym zaimplementowano 16-bitowy komputer retro czytający oprogramowanie z kart SD.

fpga firmware retro verilog retrocomputing retrogaming verilog-hdl verilog-project

Updated Apr 23, 2023
Verilog

sumitarohit / Array_Multiplier_project

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This is a 4*4 Array_Multiplier_project using Verilog HDL. This is successfully implemented on FPGA board.

fpga verilog-hdl fpga-board verilog-project verilog-code arraymultiplier

Updated Oct 2, 2023
Tcl

Sumit0976 / Traffic-Light-Controller

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Traffic Light Controller using Verilog done in Vivado

verilog-project verilog-code

Updated Dec 16, 2023
Verilog

irya-senshi / Multipliers-in-Verilog

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Verilog Multiplier Implementation

verilog-project multipliers booth-multiplier

Updated Dec 26, 2023
Verilog

RicardoATT / Procesador_monociclo

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RISC-V single-cycle processor written in Verilog using the Quartus tool. Implementation of bubble sort through assembly language.

microprocessor risc-v digital-design verilog-project single-cycle-processor

Updated Apr 12, 2024
Tcl

Sandy71004 / Adders---VLSI

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In this project, I conducted an in-depth comparative analysis of various adder architectures to assess their performance in terms of delay and power consumption.

vlsi adders verilog-project