An 8 input interrupt controller written in Verilog.
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Updated
Mar 22, 2012 - Verilog
An 8 input interrupt controller written in Verilog.
A coocbook of HDL (primarily Verilog) modules
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
University of Marmara, CSE3015 2018 Fall Project
5-stage pipelined 32-bit MIPS microprocessor in Verilog
Some of the projects I developed during my studies at University of Thessaly, Electrical & Computer Engineering Dpt.
A collection of digital circuits using Verilog.
digital systems
second project - Digital System
Basics of Verilog implementation
Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.
A Verilog HDL code
Practices related to the fundamental level of the programming language Verilog.
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
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