Lightweight UART core in VHDL

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and qsf files for pin assignments.

VHDL implementation of a UART transmitter module developed for the Integrated Systems Design II course (PUCRS). Includes 8-bit parallel-to-serial conversion, FSM control, baud rate selection (9600–57600 bps), synthesis scripts, testbench, and timing/power/area reports.

VHDL implementation of a UART receiver module using FSM. Supports 8-bit data reception, baud rate selection (9600–57600 bps), parallel output with enable, 100 MHz clock, and parity check. Synthesized and analyzed using Cadence Genus, with testbench, timing, power, and area reports.

A UART implementation using VHDL on Intel Quartus and ModelSim.

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and .qsf files for pin assignments