AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Updated
May 22, 2024 - SystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
A Chisel RTL generator for network-on-chip interconnects
Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research
System-on-Chip Interconnection Network - Simulation Environment (front-end)
Reconfigurable network on chip architecture for accelerating stochastic models
Optimal circulant graphs generating results dataset
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
Network-on-Chip Simulation using Noxim
A Voting Approach for Adaptive Network-on-Chip Power-Gating
Introduction about Embedded systems lab, University of Florida
UOCNS simulator in Spring enviroment
Network on Chip Implementation written in SytemVerilog
Non-intrusive packet delivery monitoring service for Networks-on-Chip (NoCs) focusing on real-time systems. Hardware verification and development in C++/SystemC using the Visual Studio 2017 IDE.
University assignment, will soon be refactored
HLS for Networks-on-Chip
GeNoC - Software implementation of the evolutionary computation method for the synthesis of quasi-optimal topologies for Networks-on-Chip
A Vivado IP of Hermes network-on-chip router with AXI streaming interfaces
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